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Fix conding stily.
[bertos.git]
/
boards
/
at91sam7x-ek
/
templates
/
at91sam7x-ek_empty
/
cfg
/
cfg_ser.h
diff --git
a/boards/at91sam7x-ek/templates/at91sam7x-ek_empty/cfg/cfg_ser.h
b/boards/at91sam7x-ek/templates/at91sam7x-ek_empty/cfg/cfg_ser.h
index 91a10e0b2d8ade049eeb03b95150797d6728a29f..e7d5cc43d9f179db1ec9d66d2fa1adcc27af6cbf 100644
(file)
--- a/
boards/at91sam7x-ek/templates/at91sam7x-ek_empty/cfg/cfg_ser.h
+++ b/
boards/at91sam7x-ek/templates/at91sam7x-ek_empty/cfg/cfg_ser.h
@@
-160,14
+160,14
@@
*
* $WIZ$ type = "enum"
* $WIZ$ value_list = "ser_order_bit"
*
* $WIZ$ type = "enum"
* $WIZ$ value_list = "ser_order_bit"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr
and not xmega32d
"
*/
#define CONFIG_SPI_DATA_ORDER SER_MSB_FIRST
/**
* SPI clock division factor.
* $WIZ$ type = "int"
*/
#define CONFIG_SPI_DATA_ORDER SER_MSB_FIRST
/**
* SPI clock division factor.
* $WIZ$ type = "int"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr
and not xmega32d
"
*/
#define CONFIG_SPI_CLOCK_DIV 16
*/
#define CONFIG_SPI_CLOCK_DIV 16
@@
-175,7
+175,7
@@
* SPI clock polarity: normal low or normal high.
* $WIZ$ type = "enum"
* $WIZ$ value_list = "ser_spi_pol"
* SPI clock polarity: normal low or normal high.
* $WIZ$ type = "enum"
* $WIZ$ value_list = "ser_spi_pol"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr
and not xmega32d
"
*/
#define CONFIG_SPI_CLOCK_POL SPI_NORMAL_LOW
*/
#define CONFIG_SPI_CLOCK_POL SPI_NORMAL_LOW
@@
-184,7
+184,7
@@
* sample on second clock edge.
* $WIZ$ type = "enum"
* $WIZ$ value_list = "ser_spi_phase"
* sample on second clock edge.
* $WIZ$ type = "enum"
* $WIZ$ value_list = "ser_spi_phase"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr
and not xmega32d
"
*/
#define CONFIG_SPI_CLOCK_PHASE SPI_SAMPLE_ON_FIRST_EDGE
*/
#define CONFIG_SPI_CLOCK_PHASE SPI_SAMPLE_ON_FIRST_EDGE