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Change filename and macros from AT91SAM3.. to SAM3.. to conform to Atmel's official...
[bertos.git]
/
boards
/
ek-lm3s1968
/
hw
/
hw_adc.h
diff --git
a/boards/ek-lm3s1968/hw/hw_adc.h
b/boards/ek-lm3s1968/hw/hw_adc.h
index 9730ed984fc36def26bec5cbd23f02d9030df562..1f6aeadd6f200eaab6aa0b58214cba231df5e1e7 100644
(file)
--- a/
boards/ek-lm3s1968/hw/hw_adc.h
+++ b/
boards/ek-lm3s1968/hw/hw_adc.h
@@
-39,7
+39,7
@@
#define HW_ADC_H
#include <drv/adc.h>
#define HW_ADC_H
#include <drv/adc.h>
-#include <drv/
timer
.h>
+#include <drv/
clock_lm3s
.h>
#include <io/cm3.h>
#include <io/cm3.h>
@@
-49,29
+49,47
@@
INLINE uint16_t hw_readRawTemp(void)
{
/* Trig the temperature sampling */
INLINE uint16_t hw_readRawTemp(void)
{
/* Trig the temperature sampling */
- HWREG(ADC0_BASE + ADC_O_PSSI) = BV(3);
+ HWREG(ADC0_BASE + ADC_O_PSSI) |= ADC_PSSI_SS3;
+
+ /* Poll untill acquisition end */
+ while (!(HWREG(ADC0_BASE + ADC_O_SSFSTAT3) & ADC_SSFSTAT3_FULL));
return (uint16_t)HWREG(ADC0_BASE + ADC_O_SSFIFO3);
}
return (uint16_t)HWREG(ADC0_BASE + ADC_O_SSFIFO3);
}
-INLINE void hw_initIntTemp(void)
+/*
+ * Return the cpu core temperature in degrees C*100
+ */
+INLINE uint16_t hw_readIntTemp(void)
{
{
+ /* Trig the temperature sampling */
+ HWREG(ADC0_BASE + ADC_O_PSSI) |= ADC_PSSI_SS3;
+
+ /* Poll untill acquisition end */
+ while (!(HWREG(ADC0_BASE + ADC_O_SSFSTAT3) & ADC_SSFSTAT3_FULL));
+ return (uint16_t)(14750 - ADC_RANGECONV(HWREG(ADC0_BASE + ADC_O_SSFIFO3), 0, 300) * 75);
+}
+
+INLINE void hw_initIntTemp(void)
+{
+ /* Enable ADC0 clock */
SYSCTL_RCGC0_R |= SYSCTL_RCGC0_ADC0;
SYSCTL_RCGC0_R |= SYSCTL_RCGC0_ADC0;
- /* Why this??? */
- timer_udelay(1);
+ /*
+ * We wait some time because the clock is istable
+ * and that could cause system hardfault
+ */
+ lm3s_busyWait(10);
/* Disable all sequence */
HWREG(ADC0_BASE + ADC_O_ACTSS) = 0;
/* Set trigger event to programmed (for all sequence) */
HWREG(ADC0_BASE + ADC_O_EMUX) = 0;
/* Disable all sequence */
HWREG(ADC0_BASE + ADC_O_ACTSS) = 0;
/* Set trigger event to programmed (for all sequence) */
HWREG(ADC0_BASE + ADC_O_EMUX) = 0;
-
- HWREG(ADC0_BASE + ADC_O_SSMUX3) = 1;
/* Enalbe read of temperature sensor */
/* Enalbe read of temperature sensor */
- HWREG(ADC0_BASE + ADC_O_SSCTL3)
= BV(3)
;
+ HWREG(ADC0_BASE + ADC_O_SSCTL3)
|= ADC_SSCTL3_TS0
;
/* Enable sequence S03 (single sample on select channel) */
/* Enable sequence S03 (single sample on select channel) */
- HWREG(ADC0_BASE + ADC_O_ACTSS)
= BV(3)
;
+ HWREG(ADC0_BASE + ADC_O_ACTSS)
|= ADC_ACTSS_ASEN3
;
}
#endif /* HW_ADC_H */
}
#endif /* HW_ADC_H */