+#elif CPU_ARM
+
+ typedef uint32_t cpuflags_t;
+ typedef uint32_t cpustack_t;
+
+ /* Register counts include SREG too */
+ #define CPU_REG_BITS 32
+ #define CPU_REGS_CNT 16
+ #define CPU_SAVED_REGS_CNT FIXME
+ #define CPU_STACK_GROWS_UPWARD 0
+ #define CPU_SP_ON_EMPTY_SLOT 0
+ #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
+ #define CPU_HARVARD 0
+
+ #ifdef __IAR_SYSTEMS_ICC__
+
+ #include <inarm.h>
+
+ #if __CPU_MODE__ == 1 /* Thumb */
+ /* Use stubs */
+ extern cpuflags_t get_CPSR(void);
+ extern void set_CPSR(cpuflags_t flags);
+ #else
+ #define get_CPSR __get_CPSR
+ #define set_CPSR __set_CPSR
+ #endif
+
+ #define NOP __no_operation()
+ #define IRQ_DISABLE __disable_interrupt()
+ #define IRQ_ENABLE __enable_interrupt()
+
+ #define IRQ_SAVE_DISABLE(x) \
+ do { \
+ (x) = get_CPSR(); \
+ __disable_interrupt(); \
+ } while (0)
+
+ #define IRQ_RESTORE(x) \
+ do { \
+ set_CPSR(x); \
+ } while (0)
+
+ #define IRQ_GETSTATE() \
+ ((bool)(get_CPSR() & 0xb0))
+
+ #define BREAKPOINT /* asm("bkpt 0") DOES NOT WORK */
+
+ #else /* !__IAR_SYSTEMS_ICC__ */
+
+ #warning "IRQ_ macros need testing!"
+ #warning "Test now or die :-)"
+
+ #define NOP asm volatile ("mov r0,r0" ::)
+
+ #define IRQ_DISABLE \
+ do { \
+ asm volatile ( \
+ "mrs r0, cpsr\n\t" \
+ "orr r0, r0, #0xc0\n\t" \
+ "msr cpsr_c, r0" \
+ ::: "r0" \
+ ); \
+ } while (0)
+
+ #define IRQ_ENABLE \
+ do { \
+ asm volatile ( \
+ "mrs r0, cpsr\n\t" \
+ "bic r0, r0, #0xc0\n\t" \
+ "msr cpsr_c, r0" \
+ ::: "r0" \
+ ); \
+ } while (0)
+
+ #define IRQ_SAVE_DISABLE(x) \
+ do { \
+ asm volatile ( \
+ "mrs %0, cpsr\n\t" \
+ "orr r0, %0, #0xc0\n\t" \
+ "msr cpsr_c, r0" \
+ : "=r" (x) \
+ : /* no inputs */ \
+ : "r0" \
+ ); \
+ } while (0)
+
+ #define IRQ_RESTORE(x) \
+ do { \
+ asm volatile ( \
+ "msr cpsr_c, %0" \
+ : /* no outputs */ \
+ : "r" (x) \
+ ); \
+ } while (0)
+
+ #define IRQ_GETSTATE() \
+ ({ \
+ uint32_t sreg; \
+ asm volatile ( \
+ "mrs %0, cpsr\n\t" \
+ : "=r" (sreg) \
+ : /* no inputs */ \
+ ); \
+ !((sreg & 0xc0) == 0xc0); \
+ })
+
+ #endif /* !__IAR_SYSTEMS_ICC_ */
+