+#ifndef SER_UART0_IRQ_INIT
+ /**
+ * Default IRQ INIT macro - invoked in uart0_init()
+ *
+ * - Disable all interrupt
+ * - Register USART0 interrupt
+ * - Enable USART0 clock.
+ */
+ #define SER_UART0_IRQ_INIT do { \
+ US0_IDR = 0xFFFFFFFF; \
+ /* Set the vector. */ \
+ AIC_SVR(US0_ID) = uart0_irq_dispatcher; \
+ /* Initialize to edge triggered with defined priority. */ \
+ AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED; \
+ /* Enable the USART IRQ */ \
+ AIC_IECR = BV(US0_ID); \
+ PMC_PCER = BV(US0_ID); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXINIT
+ /**
+ * Default TXINIT macro - invoked in uart0_init()
+ *
+ * - Disable GPIO on USART0 tx/rx pins
+ * - Reset USART0
+ * - Set serial param: mode Normal, 8bit data, 1bit stop
+ * - Enable both the receiver and the transmitter
+ * - Enable only the RX complete interrupt
+ */
+ #if CPU_ARM_AT91
+ #define SER_UART0_BUS_TXINIT do { \
+ PIOA_PDR = BV(5) | BV(6);\
+ US0_CR = BV(US_RSTRX) | BV(US_RSTTX); \
+ US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
+ US0_CR = BV(US_RXEN) | BV(US_TXEN); \
+ US0_IER = BV(US_RXRDY); \
+ } while (0)
+ /*#elif Add other ARM families here */
+ #else
+ #error Unknown CPU
+ #endif
+
+#endif
+
+#ifndef SER_UART0_BUS_TXBEGIN
+ /**
+ * Invoked before starting a transmission
+ *
+ * - Enable both the receiver and the transmitter
+ * - Enable both the RX complete and TX empty interrupts
+ */
+ #define SER_UART0_BUS_TXBEGIN do { \
+ US0_CR = BV(US_RXEN) | BV(US_TXEN); \
+ US0_IER = BV(US_TXRDY) | BV(US_RXRDY); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXCHAR
+ /**
+ * Invoked to send one character.
+ */
+ #define SER_UART0_BUS_TXCHAR(c) do { \
+ US0_THR = c; \
+ } while (0)
+#endif