-
-
-/*
- * Interrupt handlers
- */
-
-#if CONFIG_SER_HWHANDSHAKE
-
-/// This interrupt is triggered when the CTS line goes high
-SIGNAL(SIG_CTS)
-{
- // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
- EIMSK &= ~EIMSKF_CTS;
-}
-
-#endif // CONFIG_SER_HWHANDSHAKE
-
-
-/**
- * Serial 0 TX interrupt handler
- */
-SIGNAL(USART0_UDRE_vect)
-{
- SER_STROBE_ON;
-
- struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
-
- if (fifo_isempty(txfifo))
- {
- SER_UART0_BUS_TXEND;
-#ifndef SER_UART0_BUS_TXOFF
- UARTDescs[SER_UART0].sending = false;
-#endif
- }
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
- else if (!IS_CTS_ON)
- {
- // Disable rx interrupt and tx, enable CTS interrupt
- // UNTESTED
- UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
- EIFR |= EIMSKF_CTS;
- EIMSK |= EIMSKF_CTS;
- }
-#endif
- else
- {
- char c = fifo_pop(txfifo);
- SER_UART0_BUS_TXCHAR(c);
- }
-
- SER_STROBE_OFF;
-}
-
-#ifdef SER_UART0_BUS_TXOFF
-/**
- * Serial port 0 TX complete interrupt handler.
- *
- * This IRQ is usually disabled. The UDR-empty interrupt
- * enables it when there's no more data to transmit.
- * We need to wait until the last character has been
- * transmitted before switching the 485 transceiver to
- * receive mode.
- *
- * The txfifo might have been refilled by putchar() while
- * we were waiting for the transmission complete interrupt.
- * In this case, we must restart the UDR empty interrupt,
- * otherwise we'd stop the serial port with some data
- * still pending in the buffer.
- */
-SIGNAL(SIG_UART0_TRANS)
-{
- SER_STROBE_ON;
-
- struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
- if (fifo_isempty(txfifo))
- {
- SER_UART0_BUS_TXOFF;
- UARTDescs[SER_UART0].sending = false;
- }
- else
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
-
- SER_STROBE_OFF;
-}
-#endif /* SER_UART0_BUS_TXOFF */
-
-
-#if AVR_HAS_UART1
-
-/**
- * Serial 1 TX interrupt handler
- */
-SIGNAL(USART1_UDRE_vect)
-{
- SER_STROBE_ON;
-
- struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
-
- if (fifo_isempty(txfifo))
- {
- SER_UART1_BUS_TXEND;
-#ifndef SER_UART1_BUS_TXOFF
- UARTDescs[SER_UART1].sending = false;
-#endif
- }
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
- else if (!IS_CTS_ON)
- {
- // Disable rx interrupt and tx, enable CTS interrupt
- // UNTESTED
- UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
- EIFR |= EIMSKF_CTS;
- EIMSK |= EIMSKF_CTS;
- }
-#endif
- else
- {
- char c = fifo_pop(txfifo);
- SER_UART1_BUS_TXCHAR(c);
- }
-
- SER_STROBE_OFF;
-}
-
-#ifdef SER_UART1_BUS_TXOFF
-/**
- * Serial port 1 TX complete interrupt handler.
- *
- * \sa port 0 TX complete handler.
- */
-SIGNAL(SIG_UART1_TRANS)
-{
- SER_STROBE_ON;
-
- struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
- if (fifo_isempty(txfifo))
- {
- SER_UART1_BUS_TXOFF;
- UARTDescs[SER_UART1].sending = false;
- }
- else
- UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
-
- SER_STROBE_OFF;
-}
-#endif /* SER_UART1_BUS_TXOFF */
-
-#endif // AVR_HAS_UART1
-
-
-/**
- * Serial 0 RX complete interrupt handler.
- *
- * This handler is interruptible.
- * Interrupt are reenabled as soon as recv complete interrupt is
- * disabled. Using INTERRUPT() is troublesome when the serial
- * is heavily loaded, because an interrupt could be retriggered
- * when executing the handler prologue before RXCIE is disabled.
- *
- * \note The code that re-enables interrupts is commented out
- * because in some nasty cases the interrupt is retriggered.
- * This is probably due to the RXC flag being set before
- * RXCIE is cleared. Unfortunately the RXC flag is read-only
- * and can't be cleared by code.
- */
-SIGNAL(USART0_RX_vect)
-{
- SER_STROBE_ON;
-
- /* Disable Recv complete IRQ */
- //UCSR0B &= ~BV(RXCIE);
- //IRQ_ENABLE;
-
- /* Should be read before UDR */
- ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
-
- /* To clear the RXC flag we must _always_ read the UDR even when we're
- * not going to accept the incoming data, otherwise a new interrupt
- * will occur once the handler terminates.
- */
- char c = UDR0;
- struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
-
- if (fifo_isfull(rxfifo))
- ser_uart0->status |= SERRF_RXFIFOOVERRUN;
- else
- {
- fifo_push(rxfifo, c);
-#if CONFIG_SER_HWHANDSHAKE
- if (fifo_isfull(rxfifo))
- RTS_OFF;
-#endif
- }
-
- /* Reenable receive complete int */
- //IRQ_DISABLE;
- //UCSR0B |= BV(RXCIE);
-
- SER_STROBE_OFF;
-}
-
-
-#if AVR_HAS_UART1
-
-/**
- * Serial 1 RX complete interrupt handler.
- *
- * This handler is interruptible.
- * Interrupt are reenabled as soon as recv complete interrupt is
- * disabled. Using INTERRUPT() is troublesome when the serial
- * is heavily loaded, because an interrupt could be retriggered
- * when executing the handler prologue before RXCIE is disabled.
- *
- * \see SIGNAL(USART1_RX_vect)
- */
-SIGNAL(USART1_RX_vect)
-{
- SER_STROBE_ON;
-
- /* Disable Recv complete IRQ */
- //UCSR1B &= ~BV(RXCIE);
- //IRQ_ENABLE;
-
- /* Should be read before UDR */
- ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
-
- /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
- * not going to accept the incoming data
- */
- char c = UDR1;
- struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
- //ASSERT_VALID_FIFO(rxfifo);
-
- if (UNLIKELY(fifo_isfull(rxfifo)))
- ser_uart1->status |= SERRF_RXFIFOOVERRUN;
- else
- {
- fifo_push(rxfifo, c);
-#if CONFIG_SER_HWHANDSHAKE
- if (fifo_isfull(rxfifo))
- RTS_OFF;
-#endif
- }
- /* Re-enable receive complete int */
- //IRQ_DISABLE;
- //UCSR1B |= BV(RXCIE);
-
- SER_STROBE_OFF;
-}
-
-#endif // AVR_HAS_UART1
-
-
-/**
- * SPI interrupt handler
- */
-SIGNAL(SIG_SPI)
-{
- SER_STROBE_ON;
-
- /* Read incoming byte. */
- if (!fifo_isfull(&ser_spi->rxfifo))
- fifo_push(&ser_spi->rxfifo, SPDR);
- /*
- * FIXME
- else
- ser_spi->status |= SERRF_RXFIFOOVERRUN;
- */
-
- /* Send */
- if (!fifo_isempty(&ser_spi->txfifo))
- SPDR = fifo_pop(&ser_spi->txfifo);
- else
- UARTDescs[SER_SPI].sending = false;
-
- SER_STROBE_OFF;
-}