-#if defined(*((volatile uint32_t *)(USART_HAS_PDC)
-
-/**
- * Receive Pointer Register
- */
-/*\{*/
-#define US0_RPR (*((volatile uint32_t *)(USART0_BASE + PERIPH_RPR_OFF) ///< Channel 0 receive pointer register address.
-#define US1_RPR (*((volatile uint32_t *)(USART1_BASE + PERIPH_RPR_OFF) ///< Channel 1 receive pointer register address.
-/*\}*/
-
-/**
- * Receive Counter Register
- */
-/*\{*/
-#define US0_RCR (*((volatile uint32_t *)(USART0_BASE + PERIPH_RCR_OFF) ///< Channel 0 receive counter register address.
-#define US1_RCR (*((volatile uint32_t *)(USART1_BASE + PERIPH_RCR_OFF) ///< Channel 1 receive counter register address.
-/*\}*/
-
-/**
- * Transmit Pointer Register
- */
-/*\{*/
-#define US0_TPR (*((volatile uint32_t *)(USART0_BASE + PERIPH_TPR_OFF) ///< Channel 0 transmit pointer register address.
-#define US1_TPR (*((volatile uint32_t *)(USART1_BASE + PERIPH_TPR_OFF) ///< Channel 1 transmit pointer register address.
-/*\}*/
-
-/**
- * Name Transmit Counter Register
- */
-/*\{*/
-#define US0_TCR (*((volatile uint32_t *)(USART0_BASE + PERIPH_TCR_OFF) ///< Channel 0 transmit counter register address.
-#define US1_TCR (*((volatile uint32_t *)(USART1_BASE + PERIPH_TCR_OFF) ///< Channel 1 transmit counter register address.
-/*\}*/
-
-#if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
-#define US0_RNPR (*((volatile uint32_t *)(USART0_BASE + PERIPH_RNPR_OFF) ///< PDC channel 0 receive next pointer register.
-#define US1_RNPR (*((volatile uint32_t *)(USART1_BASE + PERIPH_RNPR_OFF) ///< PDC channel 1 receive next pointer register.
-#define US0_RNCR (*((volatile uint32_t *)(USART0_BASE + PERIPH_RNCR_OFF) ///< PDC channel 0 receive next counter register.
-#define US1_RNCR (*((volatile uint32_t *)(USART1_BASE + PERIPH_RNCR_OFF) ///< PDC channel 1 receive next counter register.
-#endif
-
-#if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
-#define US0_TNPR (*((volatile uint32_t *)(USART0_BASE + PERIPH_TNPR_OFF) ///< PDC channel 0 transmit next pointer register.
-#define US1_TNPR (*((volatile uint32_t *)(USART1_BASE + PERIPH_TNPR_OFF) ///< PDC channel 1 transmit next pointer register.
-#define US0_TNCR (*((volatile uint32_t *)(USART0_BASE + PERIPH_TNCR_OFF) ///< PDC channel 0 transmit next counter register.
-#define US1_TNCR (*((volatile uint32_t *)(USART1_BASE + PERIPH_TNCR_OFF) ///< PDC channel 1 transmit next counter register.
-#endif
-
-#if defined(PERIPH_PTCR_OFF)
-#define US0_PTCR (*((volatile uint32_t *)(USART0_BASE + PERIPH_PTCR_OFF) ///< PDC channel 0 transfer control register.
-#define US1_PTCR (*((volatile uint32_t *)(USART1_BASE + PERIPH_PTCR_OFF) ///< PDC channel 1 transfer control register.
-#endif
-
-#if defined(PERIPH_PTSR_OFF)
-#define US0_PTSR (*((volatile uint32_t *)(USART0_BASE + PERIPH_PTSR_OFF) ///< PDC channel 0 transfer status register.
-#define US1_PTSR (*((volatile uint32_t *)(USART1_BASE + PERIPH_PTSR_OFF) ///< PDC channel 1 transfer status register.
-#endif
+#if USART_HAS_PDC
+
+ /**
+ * Receive Pointer Register
+ */
+ /*\{*/
+ #define US0_RPR (*((reg32_t *)(USART0_BASE + PERIPH_RPR_OFF))) ///< Channel 0 receive pointer register address.
+ #define US1_RPR (*((reg32_t *)(USART1_BASE + PERIPH_RPR_OFF))) ///< Channel 1 receive pointer register address.
+ /*\}*/
+
+ /**
+ * Receive Counter Register
+ */
+ /*\{*/
+ #define US0_RCR (*((reg32_t *)(USART0_BASE + PERIPH_RCR_OFF))) ///< Channel 0 receive counter register address.
+ #define US1_RCR (*((reg32_t *)(USART1_BASE + PERIPH_RCR_OFF))) ///< Channel 1 receive counter register address.
+ /*\}*/
+
+ /**
+ * Transmit Pointer Register
+ */
+ /*\{*/
+ #define US0_TPR (*((reg32_t *)(USART0_BASE + PERIPH_TPR_OFF))) ///< Channel 0 transmit pointer register address.
+ #define US1_TPR (*((reg32_t *)(USART1_BASE + PERIPH_TPR_OFF))) ///< Channel 1 transmit pointer register address.
+ /*\}*/
+
+ /**
+ * Transmit Counter Register
+ */
+ /*\{*/
+ #define US0_TCR (*((reg32_t *)(USART0_BASE + PERIPH_TCR_OFF))) ///< Channel 0 transmit counter register address.
+ #define US1_TCR (*((reg32_t *)(USART1_BASE + PERIPH_TCR_OFF))) ///< Channel 1 transmit counter register address.
+ /*\}*/
+
+ #if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
+ #define US0_RNPR (*((reg32_t *)(USART0_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 0 receive next pointer register.
+ #define US1_RNPR (*((reg32_t *)(USART1_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 1 receive next pointer register.
+ #define US0_RNCR (*((reg32_t *)(USART0_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 0 receive next counter register.
+ #define US1_RNCR (*((reg32_t *)(USART1_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 1 receive next counter register.
+ #endif
+
+ #if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
+ #define US0_TNPR (*((reg32_t *)(USART0_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 0 transmit next pointer register.
+ #define US1_TNPR (*((reg32_t *)(USART1_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 1 transmit next pointer register.
+ #define US0_TNCR (*((reg32_t *)(USART0_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 0 transmit next counter register.
+ #define US1_TNCR (*((reg32_t *)(USART1_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 1 transmit next counter register.
+ #endif
+
+ #if defined(PERIPH_PTCR_OFF)
+ #define US0_PTCR (*((reg32_t *)(USART0_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 0 transfer control register.
+ #define US1_PTCR (*((reg32_t *)(USART1_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 1 transfer control register.
+ #endif
+
+ #if defined(PERIPH_PTSR_OFF)
+ #define US0_PTSR (*((reg32_t *)(USART0_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 0 transfer status register.
+ #define US1_PTSR (*((reg32_t *)(USART1_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 1 transfer status register.
+ #endif