+#endif
+#ifndef EIMSKB_CTS
+#define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
+#endif
+/*\}*/
+
+
+/*!
+ * \def CONFIG_SER_STROBE
+ *
+ * This is a debug facility that can be used to
+ * monitor SER interrupt activity on an external pin.
+ *
+ * To use strobes, redefine the macros SER_STROBE_ON,
+ * SER_STROBE_OFF and SER_STROBE_INIT and set
+ * CONFIG_SER_STROBE to 1.
+ */
+#ifndef CONFIG_SER_STROBE
+ #define SER_STROBE_ON do {/*nop*/} while(0)
+ #define SER_STROBE_OFF do {/*nop*/} while(0)
+ #define SER_STROBE_INIT do {/*nop*/} while(0)
+#endif
+
+
+/*!
+ * \name Overridable serial hooks
+ *
+ * These can be redefined in hw.h to implement
+ * special bus policies such as half-duplex, 485, etc.
+ *
+ *
+ * \code
+ * TXBEGIN TXCHAR TXEND TXOFF
+ * | __________|__________ | |
+ * | | | | | | | | |
+ * v v v v v v v v v
+ * ______ __ __ __ __ __ __ ________________
+ * \/ \/ \/ \/ \/ \/ \/
+ * ______/\__/\__/\__/\__/\__/\__/
+ *
+ * \endcode
+ *
+ * \{
+ */
+#ifndef SER_UART0_BUS_TXINIT
+ /*!
+ * Default TXINIT macro - invoked in uart0_init()
+ *
+ * - Enable both the receiver and the transmitter
+ * - Enable only the RX complete interrupt
+ */
+ #define SER_UART0_BUS_TXINIT do { \
+ UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXBEGIN
+ /*!
+ * Invoked before starting a transmission
+ *
+ * - Enable both the receiver and the transmitter
+ * - Enable both the RX complete and UDR empty interrupts
+ */
+ #define SER_UART0_BUS_TXBEGIN do { \
+ UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXCHAR
+ /*!
+ * Invoked to send one character.
+ */
+ #define SER_UART0_BUS_TXCHAR(c) do { \
+ UDR0 = (c); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXEND
+ /*!
+ * Invoked as soon as the txfifo becomes empty
+ *
+ * - Keep both the receiver and the transmitter enabled
+ * - Keep the RX complete interrupt enabled
+ * - Disable the UDR empty interrupt
+ */
+ #define SER_UART0_BUS_TXEND do { \
+ UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXOFF
+ /*!
+ * \def SER_UART0_BUS_TXOFF
+ *
+ * Invoked after the last character has been transmitted
+ *
+ * The default is no action.
+ */
+#endif
+
+#ifndef SER_UART1_BUS_TXINIT
+ /*! \sa SER_UART0_BUS_TXINIT */
+ #define SER_UART1_BUS_TXINIT do { \
+ UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
+ } while (0)
+#endif
+#ifndef SER_UART1_BUS_TXBEGIN
+ /*! \sa SER_UART0_BUS_TXBEGIN */
+ #define SER_UART1_BUS_TXBEGIN do { \
+ UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
+ } while (0)
+#endif
+#ifndef SER_UART1_BUS_TXCHAR
+ /*! \sa SER_UART0_BUS_TXCHAR */
+ #define SER_UART1_BUS_TXCHAR(c) do { \
+ UDR1 = (c); \
+ } while (0)
+#endif
+#ifndef SER_UART1_BUS_TXEND
+ /*! \sa SER_UART0_BUS_TXEND */
+ #define SER_UART1_BUS_TXEND do { \
+ UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
+ } while (0)
+#endif
+#ifndef SER_UART1_BUS_TXOFF
+ /*!
+ * \def SER_UART1_BUS_TXOFF
+ *
+ * \see SER_UART0_BUS_TXOFF
+ */
+#endif
+/*\}*/