+#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA168
+ #define REG_TIFR0 TIFR0
+ #define REG_TIFR2 TIFR2
+
+ #define REG_TIMSK0 TIMSK0
+ #define REG_TIMSK2 TIMSK2
+
+ #define REG_TCCR2A TCCR2A
+ #define REG_TCCR2B TCCR2B
+
+ #define REG_OCR2A OCR2A
+
+ #define BIT_OCF0A OCF0A
+ #define BIT_OCF2A OCF2A
+
+ #define BIT_OCIE0A OCIE0A
+ #define BIT_OCIE2A OCIE2A
+#else
+ #define REG_TIFR0 TIFR
+ #define REG_TIFR2 TIFR
+
+ #define REG_TIMSK0 TIMSK
+ #define REG_TIMSK2 TIMSK
+
+ #define REG_TCCR2A TCCR2
+ #define REG_TCCR2B TCCR2
+
+ #define REG_OCR2A OCR2
+
+ #define BIT_OCF0A OCF0
+ #define BIT_OCF2A OCF2
+
+ #define BIT_OCIE0A OCIE0
+ #define BIT_OCIE2A OCIE2
+#endif
+
+
+/** HW dependent timer initialization */