- static uint8_t count = TIMER1_OVF_COUNT;
-
- count--;
- if (!count)
- {
- timer_handler();
- count = TIMER1_OVF_COUNT;
- }
-
- #if (ARCH & ARCH_BOARD_KC)
- /*
- * Super-optimization-hack: switch CPU ADC mux here, ASAP after the start
- * of conversion (auto-triggered with timer 1 overflow).
- * The switch can be done 2 ADC cycles after start of conversion.
- * The handler prologue takes a little more than 32 CPU cycles: with
- * the prescaler at 1/16 the timing should be correct even at the start
- * of the handler.
- *
- * The switch is synchronized with the ADC handler using _adc_trigger_lock.
- */
- extern uint8_t _adc_idx_next;
- extern bool _adc_trigger_lock;
-
- if (!_adc_trigger_lock)
- {
- TIMER_STROBE_ON;
- ADC_SETCHN(_adc_idx_next);
- TIMER_STROBE_OFF;
- _adc_trigger_lock = true;
- }
- #endif
- }
-
-#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
-
- #define DEFINE_TIMER_ISR \
- SIGNAL(SIG_OUTPUT_COMPARE0)
-
-#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
+/*!
+ * System timer: additional division after the prescaler
+ * 12288000 / 64 / 192 (0..191) = 1 ms
+ */
+#define OCR_DIVISOR (((CLOCK_FREQ + TIMER_PRESCALER / 2) / TIMER_PRESCALER + TICKS_PER_SEC / 2) / TICKS_PER_SEC - 1) /* 191 */