- /*
- * Timer 1 overflow irq handler. It's called at the frequency of the timer 1
- * PWM (should be 24 kHz). It's too much for timer purposes, so the interrupt
- * handler is really a counter that call the true handler in timer.c
- * every 1 ms.
- */
- SIGNAL(SIG_OVERFLOW1)
- {
- #if (ARCH & ARCH_BOARD_KC)
- /*
- * Super-optimization-hack: switch CPU ADC mux here, ASAP after the start
- * of conversion (auto-triggered with timer 1 overflow).
- * The switch can be done 2 ADC cycles after start of conversion.
- * The handler prologue takes a little more than 32 CPU cycles: with
- * the prescaler at 1/16 the timing should be correct even at the start
- * of the handler.
- *
- * The switch is synchronized with the ADC handler using _adc_trigger_lock.
- *
- * Mel (A Real Programmer)
- */
- extern uint8_t _adc_idx_next;
- extern bool _adc_trigger_lock;
-
- if (!_adc_trigger_lock)
- {
- /*
- * Disable free-running mode to avoid starting a
- * new conversion before the ADC handler has read
- * the ongoing one. This condition could occur
- * under very high interrupt load and would have the
- * unwanted effect of reading from the wrong ADC
- * channel.
- *
- * NOTE: writing 0 to ADSC and ADIF has no effect.
- */
- ADCSRA = ADCSRA & ~(BV(ADFR) | BV(ADIF) | BV(ADSC));
-
- ADC_SETCHN(_adc_idx_next);
- _adc_trigger_lock = true;
- }
- #endif // ARCH_BOARD_KC
-
- /*!
- * How many timer overflows we must count before calling the real
- * timer handler.
- * When the timer is programmed to overflow at 24 kHz, a value of
- * 24 will result in 1ms between each call.
- */
- #define TIMER1_OVF_COUNT 24
- //#warning TIMER1_OVF_COUNT for timer at 12 kHz
- //#define TIMER1_OVF_COUNT 12
-
- static uint8_t count = TIMER1_OVF_COUNT;
-
- count--;
- if (!count)
- {
- timer_handler();
- count = TIMER1_OVF_COUNT;
- }
- }
-
-#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
-
- #define DEFINE_TIMER_ISR \
- SIGNAL(SIG_OUTPUT_COMPARE0)
-
-#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)