- /*
- * Disable free-running mode to avoid starting a
- * new conversion before the ADC handler has read
- * the ongoing one. This condition could occur
- * under very high interrupt load and would have the
- * unwanted effect of reading from the wrong ADC
- * channel.
- *
- * NOTE: writing 0 to ADSC and ADIF has no effect.
- */
- ADCSRA = ADCSRA & ~(BV(ADATE) | BV(ADIF) | BV(ADSC));
-
- ADC_SETCHN(_adc_idx_next);
- _adc_trigger_lock = true;
- }
- #endif // ARCH_BOARD_KC
-
- /*!
- * How many timer overflows we must count before calling the real
- * timer handler.
- * When the timer is programmed to overflow at 24 kHz, a value of
- * 24 will result in 1ms between each call.
- */
- #define TIMER1_OVF_COUNT 24
- //#warning TIMER1_OVF_COUNT for timer at 12 kHz
- //#define TIMER1_OVF_COUNT 12
-
- static uint8_t count = TIMER1_OVF_COUNT;
-
- count--;
- if (!count)
- {
- timer_handler();
- count = TIMER1_OVF_COUNT;
- }
- }
-
-#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
-
- #define DEFINE_TIMER_ISR \
- SIGNAL(SIG_OUTPUT_COMPARE0)
-
-#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
+/*!
+ * System timer: additional division after the prescaler
+ * 12288000 / 64 / 192 (0..191) = 1 ms
+ */
+#define OCR_DIVISOR (((CLOCK_FREQ + TIMER_PRESCALER / 2) / TIMER_PRESCALER + TICKS_PER_SEC / 2) / TICKS_PER_SEC - 1) /* 191 */