{ \
(DDRD &= ~(BV(PD4) | BV(PD5) | BV(PD6) | BV(PD7))); \
(PORTD |= (BV(PD4) | BV(PD5) | BV(PD6) | BV(PD7))); \
} while(0)
#define INPUT_INIT_E do \
{ \
(DDRD &= ~(BV(PD4) | BV(PD5) | BV(PD6) | BV(PD7))); \
(PORTD |= (BV(PD4) | BV(PD5) | BV(PD6) | BV(PD7))); \
} while(0)
#define INPUT_INIT_E do \
(DDRE &= ~(BV(PE4) | BV(PE5) | BV(PE6) | BV(PE7))); \
ATOMIC((PORTE |= (BV(PE4) | BV(PE5) | BV(PE6) | BV(PE7)))); \
} while(0)
(DDRE &= ~(BV(PE4) | BV(PE5) | BV(PE6) | BV(PE7))); \
ATOMIC((PORTE |= (BV(PE4) | BV(PE5) | BV(PE6) | BV(PE7)))); \
} while(0)