+//Define output level
+#define SCK_HIGH (PORTB |= BV(PB1))
+#define SCK_LOW (PORTB &= ~BV(PB1))
+#define SOUT_OUT_HIGH (PORTB |= BV(PB2))
+#define SOUT_OUT_LOW (PORTB &= ~BV(PB2))
+#define SLOAD_OUT_HIGH (PORTB |= BV(PB3))
+#define SLOAD_OUT_LOW (PORTB &= ~BV(PB3))
+#define OE_LOW (PORTG &= BV(PG3))
+
+/**
+ * Define the macros needed to set the serial input bit of SIPO device
+ * low or high.
+ */
+#define SIPO_SI_HIGH() SOUT_OUT_HIGH
+#define SIPO_SI_LOW() SOUT_OUT_LOW
+
+/**
+ * Drive pin to load the bit, presented in serial-in pin,
+ * into sipo shift register.
+ */
+#define SIPO_SI_CLOCK(clk_pol) \
+ do{ \
+ (void)clk_pol; \
+ SCK_HIGH; \
+ SCK_LOW; \
+ }while(0)
+
+/**
+ * Clock the content of shift register to output.
+ */
+#define SIPO_LOAD(device, load_pol) \
+ do { \
+ (void)device; \
+ (void)load_pol; \
+ SLOAD_OUT_HIGH; \
+ SLOAD_OUT_LOW; \
+ }while(0)
+
+/**
+ * Enable the shift register output.
+ */
+#define SIPO_ENABLE() OE_LOW;
+
+/**
+ * Set logic level for load signal
+ */
+#define SIPO_SET_LD_LEVEL(device, load_pol) \
+ do { \
+ (void)device; \
+ if(load_pol) \
+ SLOAD_OUT_HIGH; \
+ else \
+ SLOAD_OUT_LOW; \
+ } while (0)
+
+
+/**
+ * Sel logic level for clock signal
+ */
+#define SIPO_SET_CLK_LEVEL(clock_pol) \
+ do { \
+ if(clock_pol) \
+ SCK_HIGH; \
+ else \
+ SCK_LOW; \
+ } while (0)
+
+#define SIPO_SET_SI_LEVEL() SIPO_SI_LOW()
+
+/**
+ * Do everything needed in order to init the SIPO pins.
+ */
+#define SIPO_INIT_PIN() \
+ do { \
+ OE_OUT; \
+ SOUT_OUT; \
+ SCK_OUT; \
+ SLOAD_OUT; \
+ SIPO_ENABLE(); \
+ } while(0)