+#if CPU_REG_BITS >= CPU_BITS_PER_PTR
+
+ /*
+ * 16/32bit CPUs that can update a pointer with a single write
+ * operation, no need to disable interrupts.
+ */
+ #define fifo_isempty_locked(fb) fifo_isempty((fb))
+ #define fifo_push_locked(fb, c) fifo_push((fb), (c))
+ #define fifo_pop_locked(fb) fifo_pop((fb))
+ #define fifo_flush_locked(fb) fifo_flush((fb))
+
+#else /* CPU_REG_BITS < CPU_BITS_PER_PTR */
+
+ /**
+ * Similar to fifo_isempty(), but with stronger guarantees for
+ * concurrent access between user and interrupt code.
+ *
+ * \note This is actually only needed for 8-bit processors.
+ *
+ * \sa fifo_isempty()
+ */
+ INLINE bool fifo_isempty_locked(const FIFOBuffer *fb)
+ {
+ bool result;
+ ATOMIC(result = fifo_isempty(fb));
+ return result;
+ }
+
+
+ /**
+ * Similar to fifo_push(), but with stronger guarantees for
+ * concurrent access between user and interrupt code.
+ *
+ * \note This is actually only needed for 8-bit processors.
+ *
+ * \sa fifo_push()
+ */
+ INLINE void fifo_push_locked(FIFOBuffer *fb, unsigned char c)
+ {
+ ATOMIC(fifo_push(fb, c));
+ }
+
+ /* Probably not really needed, but hard to prove. */
+ INLINE unsigned char fifo_pop_locked(FIFOBuffer *fb)
+ {
+ unsigned char c;
+ ATOMIC(c = fifo_pop(fb));
+ return c;
+ }
+
+ /**
+ * Similar to fifo_flush(), but with stronger guarantees for
+ * concurrent access between user and interrupt code.
+ *
+ * \note This is actually only needed for 8-bit processors.
+ *
+ * \sa fifo_flush()
+ */
+ INLINE void fifo_flush_locked(FIFOBuffer *fb)
+ {
+ ATOMIC(fifo_flush(fb));
+ }
+
+#endif /* CPU_REG_BITS < BITS_PER_PTR */
+
+
+/**
+ * Thread safe version of fifo_isfull()
+ */
+INLINE bool fifo_isfull_locked(const FIFOBuffer *_fb)
+{
+ bool result;
+ ATOMIC(result = fifo_isfull(_fb));
+ return result;
+}
+
+
+/**