Add missing assert.

[bertos.git] / app / triface / cfg / cfg_ser.h

diff --git a/app/triface/cfg/cfg_ser.h b/app/triface/cfg/cfg_ser.h
index eb11a4cb55edb3ee5f37d0c5c59b74c67d43e959..c474c890e730d7bbc32d8ec61414ccb06eaba4c9 100644 (file)
--- a/app/triface/cfg/cfg_ser.h
+++ b/app/triface/cfg/cfg_ser.h
@@ -35,74 +35,78 @@
  * \version $Id$
  *
  * \author Daniele Basile <asterix@develer.com>
- */ 
+ */
 
 #ifndef CFG_SER_H
 #define CFG_SER_H
 
 
 /// Kdebug console on debug unit
-#define CONFIG_TRIFACE_PORT      0
+#define CONFIG_TRIFACE_PORT      1
 
 /// Baud-rate for the kdebug console
 #define CONFIG_TRIFACE_BAUDRATE  115200
+/// Triface serial tag port
+#define TAG_SER_PORT 0
+///Baud-rate for triface serial tag port
+#define TAG_SER_BAUDRATE 9600
 
-/// [bytes] Size of the outbound FIFO buffer for port 0. 
+/// [bytes] Size of the outbound FIFO buffer for port 0.
 #define CONFIG_UART0_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 0. 
+/// [bytes] Size of the inbound FIFO buffer for port 0.
 #define CONFIG_UART0_RXBUFSIZE  64
 
-/// [bytes] Size of the outbound FIFO buffer for port 1. 
+/// [bytes] Size of the outbound FIFO buffer for port 1.
 #define CONFIG_UART1_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 1. 
+/// [bytes] Size of the inbound FIFO buffer for port 1.
 #define CONFIG_UART1_RXBUFSIZE  64
 
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only) 
+/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only)
 #define CONFIG_SPI_TXBUFSIZE    32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only) 
+/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only)
 #define CONFIG_SPI_RXBUFSIZE    32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 0. 
+/// [bytes] Size of the outbound FIFO buffer for SPI port 0.
 #define CONFIG_SPI0_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 0. 
+/// [bytes] Size of the inbound FIFO buffer for SPI port 0.
 #define CONFIG_SPI0_RXBUFSIZE  32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 1. 
+/// [bytes] Size of the outbound FIFO buffer for SPI port 1.
 #define CONFIG_SPI1_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 1. 
+/// [bytes] Size of the inbound FIFO buffer for SPI port 1.
 #define CONFIG_SPI1_RXBUFSIZE  32
 
-/// SPI data order (AVR only). 
+/// SPI data order (AVR only).
 #define CONFIG_SPI_DATA_ORDER  SER_MSB_FIRST
 
-/// SPI clock division factor (AVR only). 
+/// SPI clock division factor (AVR only).
 #define CONFIG_SPI_CLOCK_DIV   16
 
-/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only). 
+/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only).
 #define CONFIG_SPI_CLOCK_POL   0
 
-/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only). 
+/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only).
 #define CONFIG_SPI_CLOCK_PHASE 0
 
-/// Default transmit timeout (ms). Set to -1 to disable timeout support.
-#define CONFIG_SER_TXTIMEOUT    100
+/// Default transmit timeout (ms). Set to -1 for infinite timeout, 0 for null timeout
+#define CONFIG_SER_TXTIMEOUT    0
 
-/// Default receive timeout (ms). Set to -1 to disable timeout support.
-#define CONFIG_SER_RXTIMEOUT    100
+/// Default receive timeout (ms). Set to -1 for infinite timeout, 0 for null timeout
+#define CONFIG_SER_RXTIMEOUT    0
 
-/// Use RTS/CTS handshake 
+/// Use RTS/CTS handshake
 #define CONFIG_SER_HWHANDSHAKE   0
 
 /// Default baud rate (set to 0 to disable).
 #define CONFIG_SER_DEFBAUDRATE   0
 
-/// Enable second serial port in emulator. 
+/// Enable second serial port in emulator.
 #define CONFIG_EMUL_UART1        0
 
 /**