Add error check.

[bertos.git] / app / triface / cfg / cfg_ser.h

diff --git a/app/triface/cfg/cfg_ser.h b/app/triface/cfg/cfg_ser.h
index 55efe30114a06668ad801e280a4b0ef4866a9e57..c474c890e730d7bbc32d8ec61414ccb06eaba4c9 100644 (file)
--- a/app/triface/cfg/cfg_ser.h
+++ b/app/triface/cfg/cfg_ser.h
@@ -94,11 +94,11 @@
 /// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only).
 #define CONFIG_SPI_CLOCK_PHASE 0
 
-/// Default transmit timeout (ms). Set to -1 to disable timeout support.
-#define CONFIG_SER_TXTIMEOUT    10
+/// Default transmit timeout (ms). Set to -1 for infinite timeout, 0 for null timeout
+#define CONFIG_SER_TXTIMEOUT    0
 
-/// Default receive timeout (ms). Set to -1 to disable timeout support.
-#define CONFIG_SER_RXTIMEOUT    10
+/// Default receive timeout (ms). Set to -1 for infinite timeout, 0 for null timeout
+#define CONFIG_SER_RXTIMEOUT    0
 
 /// Use RTS/CTS handshake
 #define CONFIG_SER_HWHANDSHAKE   0