Remove syslog from nightly test.

[bertos.git] / bertos / cfg / cfg_adc.h

diff --git a/bertos/cfg/cfg_adc.h b/bertos/cfg/cfg_adc.h
index 8e3e98a522e8828cd72371eaf838063c85e40db9..62ee6ed73f34bc223e71e3c0d47003c48fc3b704 100644 (file)
--- a/bertos/cfg/cfg_adc.h
+++ b/bertos/cfg/cfg_adc.h
@@ -30,32 +30,120 @@
  *
  * -->
  *
- * \brief Configuration file for ADC module.
+ * \brief Configuration file for the ADC module.
  *
- * \version $Id$
  * \author Daniele Basile <asterix@develer.com>
  */
 
 #ifndef CFG_ADC_H
 #define CFG_ADC_H
 
-/// Module logging level.
+/**
+ * Module logging level.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "log_level"
+ */
 #define ADC_LOG_LEVEL      LOG_LVL_INFO
 
-/// Module logging format.
+/**
+ * Module logging format.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "log_format"
+ */
 #define ADC_LOG_FORMAT     LOG_FMT_VERBOSE
 
+/**
+ * Clock Frequency for ADC conversion.
+ * This frequency will be rounded down to an integer
+ * submultiple of CPU_FREQ.
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "at91"
+ * $WIZ$ max = 5000000
+ */
+#define CONFIG_ADC_CLOCK        4800000UL
 
-#define CONFIG_ADC_CLOCK        4800000UL   ///< Frequency clock for ADC conversion.
-#define CONFIG_ADC_STARTUP_TIME 20          ///< Minimum time for startup a conversion in micro second.
-#define CONFIG_ADC_SHTIME       834         ///< Minimum time for sample and hold in nano second
+/**
+ * Minimum time for starting up a conversion [us].
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 20
+ * $WIZ$ supports = "at91"
+ */
+#define CONFIG_ADC_STARTUP_TIME 20
 
+/**
+ * Minimum time for sample and hold [ns].
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 600
+ * $WIZ$ supports = "at91"
+ */
+#define CONFIG_ADC_SHTIME       834
 
-#define CONFIG_ADC_AVR_REF      1   ///< ADC setting for AVR target
-#define CONFIG_ADC_AVR_DIVISOR  2   ///< ADC setting for AVR target
+/**
+ * ADC Voltage Reference.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "avr_adc_refs"
+ * $WIZ$ supports = "avr"
+ */
+#define CONFIG_ADC_AVR_REF      ADC_AVR_AVCC
 
+/**
+ * ADC clock divisor from main crystal.
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ max = 128
+ * $WIZ$ supports = "avr"
+ */
+#define CONFIG_ADC_AVR_DIVISOR  2
 
-/// Enable ADS strobe.
+/**
+ * Enable ADC strobe for debugging ADC ISR.
+ *
+ * $WIZ$ type = "boolean"
+ */
 #define CONFIG_ADC_STROBE  0
 
+
+/**
+ * Start up timer[s] = startup value / ADCClock [Hz]
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "sam3_adc_sut"
+ * $WIZ$ supports = "sam3"
+ */
+#define CONFIG_ADC_SUT         ADC_SUT512
+
+/**
+ * Analog Settling Time[s] = settling value / ADCClock[Hz]
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "sam3_adc_stt"
+ * $WIZ$ supports = "sam3"
+ */
+#define CONFIG_ADC_STTLING     ADC_AST17
+
+/**
+ * Tracking Time[s] = (TRACKTIM + 1) / ADCClock[Hz]
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 0
+ * $WIZ$ supports = "sam3"
+ */
+#define CONFIG_ADC_TRACKTIM    0
+
+/**
+ * Transfer Period[s] = (TRANSFER * 2 + 3) ADCClock[Hz]
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 0
+ * $WIZ$ supports = "sam3"
+ */
+#define CONFIG_ADC_TRANSFER    1
+
 #endif /* CFG_ADC_H */