*
* \brief Configuration file for the ADC module.
*
- * \version $Id$
* \author Daniele Basile <asterix@develer.com>
*/
/**
* Clock Frequency for ADC conversion.
+ * This frequency will be rounded down to an integer
+ * submultiple of CPU_FREQ.
*
* $WIZ$ type = "int"
* $WIZ$ supports = "at91"
+ * $WIZ$ max = 5000000
*/
#define CONFIG_ADC_CLOCK 4800000UL
* Minimum time for starting up a conversion [us].
*
* $WIZ$ type = "int"
- * $WIZ$ min = "0"
+ * $WIZ$ min = 20
* $WIZ$ supports = "at91"
*/
#define CONFIG_ADC_STARTUP_TIME 20
/**
- * Minimum time for sample and hold [us].
+ * Minimum time for sample and hold [ns].
*
* $WIZ$ type = "int"
- * $WIZ$ min = "0"
+ * $WIZ$ min = 600
* $WIZ$ supports = "at91"
*/
#define CONFIG_ADC_SHTIME 834
* ADC clock divisor from main crystal.
*
* $WIZ$ type = "int"
- * $WIZ$ min = "2"
- * $WIZ$ max = "128"
+ * $WIZ$ min = 2
+ * $WIZ$ max = 128
* $WIZ$ supports = "avr"
*/
#define CONFIG_ADC_AVR_DIVISOR 2