*
* -->
*
- * \brief Configuration file for ADC module.
+ * \brief Configuration file for the ADC module.
*
- * \version $Id$
* \author Daniele Basile <asterix@develer.com>
*/
#ifndef CFG_ADC_H
#define CFG_ADC_H
-/// Module logging level.
+/**
+ * Module logging level.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "log_level"
+ */
#define ADC_LOG_LEVEL LOG_LVL_INFO
-/// Module logging format.
+/**
+ * Module logging format.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "log_format"
+ */
#define ADC_LOG_FORMAT LOG_FMT_VERBOSE
+/**
+ * Clock Frequency for ADC conversion.
+ * This frequency will be rounded down to an integer
+ * submultiple of CPU_FREQ.
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "at91"
+ * $WIZ$ max = 5000000
+ */
+#define CONFIG_ADC_CLOCK 4800000UL
-#define CONFIG_ADC_CLOCK 4800000UL ///< Frequency clock for ADC conversion.
-#define CONFIG_ADC_STARTUP_TIME 20 ///< Minimum time for startup a conversion in micro second.
-#define CONFIG_ADC_SHTIME 834 ///< Minimum time for sample and hold in nano second
+/**
+ * Minimum time for starting up a conversion [us].
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 20
+ * $WIZ$ supports = "at91"
+ */
+#define CONFIG_ADC_STARTUP_TIME 20
+/**
+ * Minimum time for sample and hold [ns].
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 600
+ * $WIZ$ supports = "at91"
+ */
+#define CONFIG_ADC_SHTIME 834
-#define CONFIG_ADC_AVR_REF 1 ///< ADC setting for AVR target
-#define CONFIG_ADC_AVR_DIVISOR 2 ///< ADC setting for AVR target
+/**
+ * ADC Voltage Reference.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "avr_adc_refs"
+ * $WIZ$ supports = "avr"
+ */
+#define CONFIG_ADC_AVR_REF ADC_AVR_AVCC
+/**
+ * ADC clock divisor from main crystal.
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ max = 128
+ * $WIZ$ supports = "avr"
+ */
+#define CONFIG_ADC_AVR_DIVISOR 2
-/// Enable ADS strobe.
+/**
+ * Enable ADC strobe for debugging ADC ISR.
+ *
+ * $WIZ$ type = "boolean"
+ */
#define CONFIG_ADC_STROBE 0
#endif /* CFG_ADC_H */