Remove unneeded config macros; Fix ser configuration.

[bertos.git] / bertos / cfg / cfg_ser.h

diff --git a/bertos/cfg/cfg_ser.h b/bertos/cfg/cfg_ser.h
index 5d5f0ffce0da726e4c8752043936d6f99e3b3f46..2adb55eaa382e182f1d06dc738539344e657c9c4 100644 (file)
--- a/bertos/cfg/cfg_ser.h
+++ b/bertos/cfg/cfg_ser.h
@@ -35,74 +35,108 @@
  * \version $Id$
  *
  * \author Daniele Basile <asterix@develer.com>
- */ 
+ */
 
 #ifndef CFG_SER_H
 #define CFG_SER_H
 
+/**
+ * Example of setting for serial port and
+ * spi port.
+ * Edit these define for your project.
+ */
 
-/// [bytes] Size of the outbound FIFO buffer for port 0. 
+/// [bytes] Size of the outbound FIFO buffer for port 0. $WIZ$ type = "int"
 #define CONFIG_UART0_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 0. 
+/// [bytes] Size of the inbound FIFO buffer for port 0. $WIZ$ type = "int"
 #define CONFIG_UART0_RXBUFSIZE  32
 
-/// [bytes] Size of the outbound FIFO buffer for port 1. 
+/// [bytes] Size of the outbound FIFO buffer for port 1. $WIZ$ type = "int"
 #define CONFIG_UART1_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 1. 
+/// [bytes] Size of the inbound FIFO buffer for port 1. $WIZ$ type = "int"
 #define CONFIG_UART1_RXBUFSIZE  32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 0. 
+
+/**
+ * [bytes] Size of the outbound FIFO buffer for SPI port.
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "avr"
+ */
+#define CONFIG_SPI_TXBUFSIZE    32
+
+/**
+ * [bytes] Size of the inbound FIFO buffer for SPI port.
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "avr"
+ */
+#define CONFIG_SPI_RXBUFSIZE    32
+
+/// [bytes] Size of the outbound FIFO buffer for SPI port 0. $WIZ$ type = "int"
 #define CONFIG_SPI0_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 0. 
+/// [bytes] Size of the inbound FIFO buffer for SPI port 0. $WIZ$ type = "int"
 #define CONFIG_SPI0_RXBUFSIZE  32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 1. 
+/// [bytes] Size of the outbound FIFO buffer for SPI port 1. $WIZ$ type = "int"
 #define CONFIG_SPI1_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 1. 
+/// [bytes] Size of the inbound FIFO buffer for SPI port 1. $WIZ$ type = "int"
 #define CONFIG_SPI1_RXBUFSIZE  32
 
-/// SPI data order (AVR only). 
+/**
+ * SPI data order.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_order_bit"
+ * $WIZ$ supports = "avr"
+ */
 #define CONFIG_SPI_DATA_ORDER  SER_MSB_FIRST
 
-/// SPI clock division factor (AVR only). 
+/**
+ * SPI clock division factor.
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "avr"
+ */
 #define CONFIG_SPI_CLOCK_DIV   16
 
-/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only). 
-#define CONFIG_SPI_CLOCK_POL   0
+/**
+ * SPI clock polarity: normal low or normal high.
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_spi_pol"
+ * $WIZ$ supports = "avr"
+ */
+#define CONFIG_SPI_CLOCK_POL        SPI_NORMAL_LOW
 
-/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only). 
-#define CONFIG_SPI_CLOCK_PHASE 0
+/**
+ * SPI clock phase you can choose sample on first edge or
+ * sample on second clock edge.
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_spi_phase"
+ * $WIZ$ supports = "avr"
+ */
+#define CONFIG_SPI_CLOCK_PHASE     SPI_SAMPLE_ON_FIRST_EDGE
 
-/// Default transmit timeout (ms). Set to -1 to disable timeout support.
+/// Default transmit timeout (ms). Set to -1 to disable timeout support. $WIZ$ type = "int"
 #define CONFIG_SER_TXTIMEOUT    -1
 
-/// Default receive timeout (ms). Set to -1 to disable timeout support.
+/// Default receive timeout (ms). Set to -1 to disable timeout support. $WIZ$ type = "int"
 #define CONFIG_SER_RXTIMEOUT    -1
 
-/// Use RTS/CTS handshake 
+/// Use RTS/CTS handshake. $WIZ$ type = "boolean"
 #define CONFIG_SER_HWHANDSHAKE   0
 
-/// Default baud rate (set to 0 to disable).
+/// Default baud rate (set to 0 to disable). $WIZ$ type = "boolean"
 #define CONFIG_SER_DEFBAUDRATE   0
 
-/// Enable ser_gets() and ser_gets_echo().
+/// Enable ser_gets() and ser_gets_echo(). $WIZ$ type = "boolean"
 #define CONFIG_SER_GETS          0
 
-/// Enable second serial port in emulator. 
+/// Enable second serial port in emulator. $WIZ$ type = "boolean"
 #define CONFIG_EMUL_UART1        0
 
-/**
- * Transmit always something on serial port 0 TX
- * to avoid interference when sending burst of data,
- * using AVR multiprocessor serial mode
- */
-#define CONFIG_SER_TXFILL        0
-
-/// For serial debug.
+/// For serial debug. $WIZ$ type = "boolean"
 #define CONFIG_SER_STROBE        0
 
 #endif /* CFG_SER_H */