Merged from external project:

[bertos.git] / bertos / cfg / cfg_ser.h

diff --git a/bertos/cfg/cfg_ser.h b/bertos/cfg/cfg_ser.h
index 75f72afa99d16667f4e9b57de97d0f0182534118..8fc59489ef9ec52eca83742c2ae4a8605345705f 100644 (file)
--- a/bertos/cfg/cfg_ser.h
+++ b/bertos/cfg/cfg_ser.h
@@ -35,53 +35,66 @@
  * \version $Id$
  *
  * \author Daniele Basile <asterix@develer.com>
- */ 
+ */
 
 #ifndef CFG_SER_H
 #define CFG_SER_H
 
+/**
+ * Example of setting for serial port and
+ * spi port.
+ * Edit these define for your project.
+ */
+/// Serial settings
+#define CONFIG_SER_PORT      0
+#define CONFIG_SER_BAUDRATE  115200
+
+/// Spi settings
+#define CONFIG_SPI_PORT      SER_SPI0
+#define CONFIG_SPI_BAUDRATE  5000000UL
+
 
-/// [bytes] Size of the outbound FIFO buffer for port 0. 
+/// [bytes] Size of the outbound FIFO buffer for port 0.
 #define CONFIG_UART0_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 0. 
+/// [bytes] Size of the inbound FIFO buffer for port 0.
 #define CONFIG_UART0_RXBUFSIZE  32
 
-/// [bytes] Size of the outbound FIFO buffer for port 1. 
+/// [bytes] Size of the outbound FIFO buffer for port 1.
 #define CONFIG_UART1_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 1. 
+/// [bytes] Size of the inbound FIFO buffer for port 1.
 #define CONFIG_UART1_RXBUFSIZE  32
 
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only) 
+/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only)
 #define CONFIG_SPI_TXBUFSIZE    32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only) 
+/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only)
 #define CONFIG_SPI_RXBUFSIZE    32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 0. 
+/// [bytes] Size of the outbound FIFO buffer for SPI port 0.
 #define CONFIG_SPI0_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 0. 
+/// [bytes] Size of the inbound FIFO buffer for SPI port 0.
 #define CONFIG_SPI0_RXBUFSIZE  32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 1. 
+/// [bytes] Size of the outbound FIFO buffer for SPI port 1.
 #define CONFIG_SPI1_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 1. 
+/// [bytes] Size of the inbound FIFO buffer for SPI port 1.
 #define CONFIG_SPI1_RXBUFSIZE  32
 
-/// SPI data order (AVR only). 
+/// SPI data order (AVR only).
 #define CONFIG_SPI_DATA_ORDER  SER_MSB_FIRST
 
-/// SPI clock division factor (AVR only). 
+/// SPI clock division factor (AVR only).
 #define CONFIG_SPI_CLOCK_DIV   16
 
-/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only). 
+/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only).
 #define CONFIG_SPI_CLOCK_POL   0
 
-/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only). 
+/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only).
 #define CONFIG_SPI_CLOCK_PHASE 0
 
 /// Default transmit timeout (ms). Set to -1 to disable timeout support.
@@ -90,7 +103,7 @@
 /// Default receive timeout (ms). Set to -1 to disable timeout support.
 #define CONFIG_SER_RXTIMEOUT    -1
 
-/// Use RTS/CTS handshake 
+/// Use RTS/CTS handshake
 #define CONFIG_SER_HWHANDSHAKE   0
 
 /// Default baud rate (set to 0 to disable).
@@ -99,7 +112,7 @@
 /// Enable ser_gets() and ser_gets_echo().
 #define CONFIG_SER_GETS          0
 
-/// Enable second serial port in emulator. 
+/// Enable second serial port in emulator.
 #define CONFIG_EMUL_UART1        0
 
 /**