Update benchmark projects.

[bertos.git] / bertos / cfg / cfg_ser.h

diff --git a/bertos/cfg/cfg_ser.h b/bertos/cfg/cfg_ser.h
index 4fc85e37530a830641beb617b6dad00ed0617312..e7d5cc43d9f179db1ec9d66d2fa1adcc27af6cbf 100644 (file)
--- a/bertos/cfg/cfg_ser.h
+++ b/bertos/cfg/cfg_ser.h
@@ -32,8 +32,6 @@
  *
  * \brief Configuration file for serial module.
  *
- * \version $Id$
- *
  * \author Daniele Basile <asterix@develer.com>
  */
 
@@ -49,46 +47,78 @@
 /**
  * Size of the outbound FIFO buffer for port 0 [bytes].
  * $WIZ$ type = "int"
- * $WIZ$ min = "2"
+ * $WIZ$ min = 2
  */
 #define CONFIG_UART0_TXBUFSIZE  32
 
 /**
  * Size of the inbound FIFO buffer for port 0 [bytes].
  * $WIZ$ type = "int"
- * $WIZ$ min = "2"
+ * $WIZ$ min = 2
  */
 #define CONFIG_UART0_RXBUFSIZE  32
 
 /**
  * Size of the outbound FIFO buffer for port 1 [bytes].
  * $WIZ$ type = "int"
- * $WIZ$ min = "2"
- * $WIZ$ supports = "at91 and not atmega8 and not atmega168 and not atmega32"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
  */
 #define CONFIG_UART1_TXBUFSIZE  32
 
 /**
  * Size of the inbound FIFO buffer for port 1 [bytes].
  * $WIZ$ type = "int"
- * $WIZ$ min = "2"
- * $WIZ$ supports = "at91 and not atmega8 and not atmega168 and not atmega32"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
  */
 #define CONFIG_UART1_RXBUFSIZE  32
 
+/**
+ * Size of the outbound FIFO buffer for port 2 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2"
+ */
+#define CONFIG_UART2_TXBUFSIZE  32
+
+/**
+ * Size of the inbound FIFO buffer for port 2 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2"
+ */
+#define CONFIG_UART2_RXBUFSIZE  32
+
+/**
+ * Size of the outbound FIFO buffer for port 3 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lpc2"
+ */
+#define CONFIG_UART3_TXBUFSIZE  32
 
 /**
- * [bytes] Size of the outbound FIFO buffer for SPI port.
+ * Size of the inbound FIFO buffer for port 3 [bytes].
  * $WIZ$ type = "int"
- * $WIZ$ min = "2"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lpc2"
+ */
+#define CONFIG_UART3_RXBUFSIZE  32
+
+
+/**
+ * Size of the outbound FIFO buffer for SPI port [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
  * $WIZ$ supports = "avr"
  */
 #define CONFIG_SPI_TXBUFSIZE    32
 
 /**
- * [bytes] Size of the inbound FIFO buffer for SPI port.
+ * Size of the inbound FIFO buffer for SPI port [bytes].
  * $WIZ$ type = "int"
- * $WIZ$ min = "2"
+ * $WIZ$ min = 2
  * $WIZ$ supports = "avr"
  */
 #define CONFIG_SPI_RXBUFSIZE    32
@@ -96,7 +126,7 @@
 /**
  * Size of the outbound FIFO buffer for SPI port 0 [bytes].
  * $WIZ$ type = "int"
- * $WIZ$ min = "2"
+ * $WIZ$ min = 2
  * $WIZ$ supports = "at91"
  */
 #define CONFIG_SPI0_TXBUFSIZE  32
@@ -104,7 +134,7 @@
 /**
  * Size of the inbound FIFO buffer for SPI port 0 [bytes].
  * $WIZ$ type = "int"
- * $WIZ$ min = "2"
+ * $WIZ$ min = 2
  * $WIZ$ supports = "at91"
  */
 #define CONFIG_SPI0_RXBUFSIZE  32
@@ -112,7 +142,7 @@
 /**
  * Size of the outbound FIFO buffer for SPI port 1 [bytes].
  * $WIZ$ type = "int"
- * $WIZ$ min = "2"
+ * $WIZ$ min = 2
  * $WIZ$ supports = "at91"
  */
 #define CONFIG_SPI1_TXBUFSIZE  32
@@ -120,7 +150,7 @@
 /**
  * Size of the inbound FIFO buffer for SPI port 1 [bytes].
  * $WIZ$ type = "int"
- * $WIZ$ min = "2"
+ * $WIZ$ min = 2
  * $WIZ$ supports = "at91"
  */
 #define CONFIG_SPI1_RXBUFSIZE  32
@@ -130,14 +160,14 @@
  *
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_order_bit"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr and not xmega32d"
  */
 #define CONFIG_SPI_DATA_ORDER  SER_MSB_FIRST
 
 /**
  * SPI clock division factor.
  * $WIZ$ type = "int"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr and not xmega32d"
  */
 #define CONFIG_SPI_CLOCK_DIV   16
 
@@ -145,7 +175,7 @@
  * SPI clock polarity: normal low or normal high.
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_spi_pol"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr and not xmega32d"
  */
 #define CONFIG_SPI_CLOCK_POL        SPI_NORMAL_LOW
 
@@ -154,35 +184,39 @@
  * sample on second clock edge.
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_spi_phase"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr and not xmega32d"
  */
 #define CONFIG_SPI_CLOCK_PHASE     SPI_SAMPLE_ON_FIRST_EDGE
 
 /**
  * Default transmit timeout (ms). Set to -1 to disable timeout support.
  * $WIZ$ type = "int"
- * $WIZ$ min = "-1"
+ * $WIZ$ min = -1
  */
 #define CONFIG_SER_TXTIMEOUT    -1
 
 /**
  * Default receive timeout (ms). Set to -1 to disable timeout support.
  * $WIZ$ type = "int"
- * $WIZ$ min = "-1"
+ * $WIZ$ min = -1
  */
 #define CONFIG_SER_RXTIMEOUT    -1
 
-/// Use RTS/CTS handshake. $WIZ$ type = "boolean"
+/**
+ * Use RTS/CTS handshake.
+ * $WIZ$ type = "boolean"
+ * $WIZ$ supports = "False"
+ */
 #define CONFIG_SER_HWHANDSHAKE   0
 
 /**
- * Default baud rate for all serial ports (set to 0 to disable).
+ * Default baudrate for all serial ports (set to 0 to disable).
  * $WIZ$ type = "int"
- * $WIZ$ min = "0"
+ * $WIZ$ min = 0
  */
 #define CONFIG_SER_DEFBAUDRATE   0UL
 
-/// Enable strobe pin for serial debug. $WIZ$ type = "boolean"
+/// Enable strobe pin for debugging serial interrupt. $WIZ$ type = "boolean"
 #define CONFIG_SER_STROBE        0
 
 #endif /* CFG_SER_H */