*
* \brief Configuration file for serial module.
*
- * \version $Id$
- *
* \author Daniele Basile <asterix@develer.com>
- */
+ */
#ifndef CFG_SER_H
#define CFG_SER_H
* spi port.
* Edit these define for your project.
*/
-/// Serial settings
-#define CONFIG_SER_PORT 0
-#define CONFIG_SER_BAUDRATE 115200
-
-/// Spi settings
-#define CONFIG_SPI_PORT 0
-#define CONFIG_SPI_BAUDRATE 5000000UL
-
-/// [bytes] Size of the outbound FIFO buffer for port 0.
+/**
+ * Size of the outbound FIFO buffer for port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ */
#define CONFIG_UART0_TXBUFSIZE 32
-/// [bytes] Size of the inbound FIFO buffer for port 0.
+/**
+ * Size of the inbound FIFO buffer for port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ */
#define CONFIG_UART0_RXBUFSIZE 32
-/// [bytes] Size of the outbound FIFO buffer for port 1.
+/**
+ * Size of the outbound FIFO buffer for port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
+ */
#define CONFIG_UART1_TXBUFSIZE 32
-/// [bytes] Size of the inbound FIFO buffer for port 1.
+/**
+ * Size of the inbound FIFO buffer for port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
+ */
#define CONFIG_UART1_RXBUFSIZE 32
+/**
+ * Size of the outbound FIFO buffer for port 2 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2"
+ */
+#define CONFIG_UART2_TXBUFSIZE 32
-/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only)
+/**
+ * Size of the inbound FIFO buffer for port 2 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2"
+ */
+#define CONFIG_UART2_RXBUFSIZE 32
+
+/**
+ * Size of the outbound FIFO buffer for port 3 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lpc2"
+ */
+#define CONFIG_UART3_TXBUFSIZE 32
+
+/**
+ * Size of the inbound FIFO buffer for port 3 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lpc2"
+ */
+#define CONFIG_UART3_RXBUFSIZE 32
+
+
+/**
+ * Size of the outbound FIFO buffer for SPI port [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "avr"
+ */
#define CONFIG_SPI_TXBUFSIZE 32
-/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only)
+/**
+ * Size of the inbound FIFO buffer for SPI port [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "avr"
+ */
#define CONFIG_SPI_RXBUFSIZE 32
-/// [bytes] Size of the outbound FIFO buffer for SPI port 0.
+/**
+ * Size of the outbound FIFO buffer for SPI port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "at91"
+ */
#define CONFIG_SPI0_TXBUFSIZE 32
-/// [bytes] Size of the inbound FIFO buffer for SPI port 0.
+/**
+ * Size of the inbound FIFO buffer for SPI port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "at91"
+ */
#define CONFIG_SPI0_RXBUFSIZE 32
-/// [bytes] Size of the outbound FIFO buffer for SPI port 1.
+/**
+ * Size of the outbound FIFO buffer for SPI port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "at91"
+ */
#define CONFIG_SPI1_TXBUFSIZE 32
-/// [bytes] Size of the inbound FIFO buffer for SPI port 1.
+/**
+ * Size of the inbound FIFO buffer for SPI port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "at91"
+ */
#define CONFIG_SPI1_RXBUFSIZE 32
-/// SPI data order (AVR only).
+/**
+ * SPI data order.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_order_bit"
+ * $WIZ$ supports = "avr and not xmega32d"
+ */
#define CONFIG_SPI_DATA_ORDER SER_MSB_FIRST
-/// SPI clock division factor (AVR only).
+/**
+ * SPI clock division factor.
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "avr and not xmega32d"
+ */
#define CONFIG_SPI_CLOCK_DIV 16
-/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only).
-#define CONFIG_SPI_CLOCK_POL 0
+/**
+ * SPI clock polarity: normal low or normal high.
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_spi_pol"
+ * $WIZ$ supports = "avr and not xmega32d"
+ */
+#define CONFIG_SPI_CLOCK_POL SPI_NORMAL_LOW
-/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only).
-#define CONFIG_SPI_CLOCK_PHASE 0
+/**
+ * SPI clock phase you can choose sample on first edge or
+ * sample on second clock edge.
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_spi_phase"
+ * $WIZ$ supports = "avr and not xmega32d"
+ */
+#define CONFIG_SPI_CLOCK_PHASE SPI_SAMPLE_ON_FIRST_EDGE
-/// Default transmit timeout (ms). Set to -1 to disable timeout support.
+/**
+ * Default transmit timeout (ms). Set to -1 to disable timeout support.
+ * $WIZ$ type = "int"
+ * $WIZ$ min = -1
+ */
#define CONFIG_SER_TXTIMEOUT -1
-/// Default receive timeout (ms). Set to -1 to disable timeout support.
+/**
+ * Default receive timeout (ms). Set to -1 to disable timeout support.
+ * $WIZ$ type = "int"
+ * $WIZ$ min = -1
+ */
#define CONFIG_SER_RXTIMEOUT -1
-/// Use RTS/CTS handshake
+/**
+ * Use RTS/CTS handshake.
+ * $WIZ$ type = "boolean"
+ * $WIZ$ supports = "False"
+ */
#define CONFIG_SER_HWHANDSHAKE 0
-/// Default baud rate (set to 0 to disable).
-#define CONFIG_SER_DEFBAUDRATE 0
-
-/// Enable ser_gets() and ser_gets_echo().
-#define CONFIG_SER_GETS 0
-
-/// Enable second serial port in emulator.
-#define CONFIG_EMUL_UART1 0
-
/**
- * Transmit always something on serial port 0 TX
- * to avoid interference when sending burst of data,
- * using AVR multiprocessor serial mode
+ * Default baudrate for all serial ports (set to 0 to disable).
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 0
*/
-#define CONFIG_SER_TXFILL 0
+#define CONFIG_SER_DEFBAUDRATE 0UL
-/// For serial debug.
+/// Enable strobe pin for debugging serial interrupt. $WIZ$ type = "boolean"
#define CONFIG_SER_STROBE 0
#endif /* CFG_SER_H */
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