Update benchmark projects.

[bertos.git] / bertos / cfg / cfg_ser.h

diff --git a/bertos/cfg/cfg_ser.h b/bertos/cfg/cfg_ser.h
index dba27153e76253c6ef58df64388f0a8a835df181..e7d5cc43d9f179db1ec9d66d2fa1adcc27af6cbf 100644 (file)
--- a/bertos/cfg/cfg_ser.h
+++ b/bertos/cfg/cfg_ser.h
@@ -32,8 +32,6 @@
  *
  * \brief Configuration file for serial module.
  *
- * \version $Id$
- *
  * \author Daniele Basile <asterix@develer.com>
  */
 
@@ -64,7 +62,7 @@
  * Size of the outbound FIFO buffer for port 1 [bytes].
  * $WIZ$ type = "int"
  * $WIZ$ min = 2
- * $WIZ$ supports = "at91 and not atmega8 and not atmega168 and not atmega32"
+ * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
  */
 #define CONFIG_UART1_TXBUFSIZE  32
 
@@ -72,7 +70,7 @@
  * Size of the inbound FIFO buffer for port 1 [bytes].
  * $WIZ$ type = "int"
  * $WIZ$ min = 2
- * $WIZ$ supports = "at91 and not atmega8 and not atmega168 and not atmega32"
+ * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
  */
 #define CONFIG_UART1_RXBUFSIZE  32
 
@@ -80,7 +78,7 @@
  * Size of the outbound FIFO buffer for port 2 [bytes].
  * $WIZ$ type = "int"
  * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s"
+ * $WIZ$ supports = "lm3s or lpc2"
  */
 #define CONFIG_UART2_TXBUFSIZE  32
 
@@ -88,10 +86,26 @@
  * Size of the inbound FIFO buffer for port 2 [bytes].
  * $WIZ$ type = "int"
  * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s"
+ * $WIZ$ supports = "lm3s or lpc2"
  */
 #define CONFIG_UART2_RXBUFSIZE  32
 
+/**
+ * Size of the outbound FIFO buffer for port 3 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lpc2"
+ */
+#define CONFIG_UART3_TXBUFSIZE  32
+
+/**
+ * Size of the inbound FIFO buffer for port 3 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lpc2"
+ */
+#define CONFIG_UART3_RXBUFSIZE  32
+
 
 /**
  * Size of the outbound FIFO buffer for SPI port [bytes].
@@ -146,14 +160,14 @@
  *
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_order_bit"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr and not xmega32d"
  */
 #define CONFIG_SPI_DATA_ORDER  SER_MSB_FIRST
 
 /**
  * SPI clock division factor.
  * $WIZ$ type = "int"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr and not xmega32d"
  */
 #define CONFIG_SPI_CLOCK_DIV   16
 
@@ -161,7 +175,7 @@
  * SPI clock polarity: normal low or normal high.
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_spi_pol"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr and not xmega32d"
  */
 #define CONFIG_SPI_CLOCK_POL        SPI_NORMAL_LOW
 
@@ -170,7 +184,7 @@
  * sample on second clock edge.
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_spi_phase"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr and not xmega32d"
  */
 #define CONFIG_SPI_CLOCK_PHASE     SPI_SAMPLE_ON_FIRST_EDGE