#include "adc_at91.h"
+#include <cpu/irq.h>
+
#include "cfg/cfg_adc.h"
-#include "cfg/cfg_kern.h"
+#include "cfg/cfg_proc.h"
+#include "cfg/cfg_signal.h"
#include <cfg/macros.h>
#include <cfg/compiler.h>
#include <io/arm.h>
-#if CONFIG_KERNEL
+#if CONFIG_KERN
#include <cfg/module.h>
#include <kern/proc.h>
#include <kern/signal.h>
ADC_IER = BV(ADC_DRDY);
}
-#endif /* CONFIG_KERNEL */
+#endif /* CONFIG_KERN */
/**
* Select mux channel \a ch.
* \todo only first 8 channels are selectable!
*/
-INLINE void adc_hw_select_ch(uint8_t ch)
+void adc_hw_select_ch(uint8_t ch)
{
//Disable all channels
ADC_CHDR = ADC_CH_MASK;
/**
* Start an ADC convertion.
* If a kernel is present, preempt until convertion is complete, otherwise
- * a busy wait on ADCS bit is done.
+ * a busy wait on ADC_DRDY bit is done.
*/
-INLINE uint16_t adc_hw_read(void)
+uint16_t adc_hw_read(void)
{
- ASSERT(!(ADC_SR & ADC_EOC_MASK));
-
- #if CONFIG_KERNEL
+ #if CONFIG_KERN
+ /* Ensure ADC is not already in use by another process */
+ ASSERT(adc_process == NULL);
adc_process = proc_current();
#endif
// Start convertion
ADC_CR = BV(ADC_START);
- #if CONFIG_KERNEL
+ #if CONFIG_KERN
// Ensure IRQs enabled.
- ASSERT(IRQ_ENABLED());
+ IRQ_ASSERT_ENABLED();
sig_wait(SIG_ADC_COMPLETE);
+
+ /* Prevent race condition in case of preemptive kernel */
+ uint16_t ret = ADC_LCDR;
+ MEMORY_BARRIER;
+ adc_process = NULL;
+ return ret;
#else
//Wait in polling until is done
while (!(ADC_SR & BV(ADC_DRDY)));
- #endif
- //Return the last converted data
- return(ADC_LCDR);
+ //Return the last converted data
+ return(ADC_LCDR);
+ #endif
}
/**
* Init ADC hardware.
*/
-INLINE void adc_hw_init(void)
+void adc_hw_init(void)
{
//Init ADC pins.
ADC_INIT_PINS();
ADC_MR |= ((ADC_COMPUTED_SHTIME << ADC_SHTIME_SHIFT) & ADC_SHTIME_MASK);
LOG_INFO("shtime[%ld]\n", (ADC_COMPUTED_SHTIME << ADC_SHTIME_SHIFT) & ADC_SHTIME_MASK);
- #if CONFIG_KERNEL
+ #if CONFIG_KERN
//Register and enable irq for adc.
adc_enable_irq();
#endif