* \brief PWM hardware-specific implementation
*
* \version $Id$
- *
* \author Daniele Basile <asterix@develer.com>
*/
#include "pwm_at91.h"
+#include "hw/pwm_map.h"
+#include <hw/hw_cpufreq.h>
+#include "cfg/cfg_pwm.h"
-#include <hw/hw_cpu.h>
+// Define logging setting (for cfg/log.h module).
+#define LOG_LEVEL PWM_LOG_LEVEL
+#define LOG_FORMAT PWM_LOG_FORMAT
+#include <cfg/log.h>
#include <cfg/macros.h>
#include <cfg/debug.h>
+
#include <io/arm.h>
-#include "appconfig.h"
/**
* Register structure for pwm driver.
{
{//PWM Channel 0
.duty_zero = false,
+ .pol = false,
.pwm_pin = BV(PWM0),
.mode_reg = &PWM_CMR0,
.duty_reg = &PWM_CDTY0,
},
{//PWM Channel 1
.duty_zero = false,
+ .pol = false,
.pwm_pin = BV(PWM1),
.mode_reg = &PWM_CMR1,
.duty_reg = &PWM_CDTY1,
},
{//PWM Channel 2
.duty_zero = false,
+ .pol = false,
.pwm_pin = BV(PWM2),
.mode_reg = &PWM_CMR2,
.duty_reg = &PWM_CDTY2,
},
{//PWM Channel 3
.duty_zero = false,
+ .pol = false,
.pwm_pin = BV(PWM3),
.mode_reg = &PWM_CMR3,
.duty_reg = &PWM_CDTY3,
for(int i = 0; i <= PWM_HW_MAX_PRESCALER_STEP; i++)
{
- period = CLOCK_FREQ / (BV(i) * freq);
-// TRACEMSG("period[%d], prescale[%d]", period, i);
+ period = CPU_FREQ / (BV(i) * freq);
+ LOG_INFO("period[%ld], prescale[%d]\n", period, i);
if ((period < PWM_HW_MAX_PERIOD) && (period != 0))
{
//Clean previous channel prescaler, and set new
}
}
- PWM_ENA = BV(dev);
-
-// TRACEMSG("PWM ch[%d] period[%d]", dev, period);
+ LOG_INFO("PWM ch[%d] period[%ld]\n", dev, period);
}
/**
ASSERT(duty <= (uint16_t)*pwm_map[dev].period_reg);
+ /*
+ * If polarity flag is true we must invert
+ * PWM polarity.
+ */
+ if (pwm_map[dev].pol)
+ {
+ duty = (uint16_t)*pwm_map[dev].period_reg - duty;
+ LOG_INFO("Inverted duty[%d], pol[%d]\n", duty, pwm_map[dev].pol);
+ }
+
/*
* WARNING: is forbidden to write 0 to duty cycle value,
* and so for duty = 0 we must enable PIO and clear output!
*/
if (!duty)
{
- PWM_PIO_PER = pwm_map[dev].pwm_pin;
+ PWM_PIO_CODR = pwm_map[dev].pwm_pin;
+ PWM_PIO_PER = pwm_map[dev].pwm_pin;
pwm_map[dev].duty_zero = true;
}
else
{
- ASSERT(PWM_CCNT0);
PWM_PIO_PDR = pwm_map[dev].pwm_pin;
+ PWM_PIO_ABSR = pwm_map[dev].pwm_pin;
+
*pwm_map[dev].update_reg = duty;
pwm_map[dev].duty_zero = false;
}
-// TRACEMSG("PWM ch[%d] duty[%d], period[%ld]", dev, duty, *pwm_map[dev].period_reg);
+ PWM_ENA = BV(dev);
+ LOG_INFO("PWM ch[%d] duty[%d], period[%ld]\n", dev, duty, *pwm_map[dev].period_reg);
}
void pwm_hw_enable(PwmDev dev)
{
if (!pwm_map[dev].duty_zero)
- PWM_PIO_PDR = pwm_map[dev].pwm_pin;
+ {
+ PWM_PIO_PDR = pwm_map[dev].pwm_pin;
+ PWM_PIO_ABSR = pwm_map[dev].pwm_pin;
+ }
}
/**
PWM_PIO_PER = pwm_map[dev].pwm_pin;
}
+/**
+ * Set PWM polarity to select pwm channel
+ */
+void pwm_hw_setPolarity(PwmDev dev, bool pol)
+{
+ pwm_map[dev].pol = pol;
+ LOG_INFO("Set pol[%d]\n", pwm_map[dev].pol);
+}
/**
* Init pwm.
* - Power on PWM
*/
PWM_PIO_CODR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
- PWM_PIO_OER = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
- PWM_PIO_PDR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
+ PWM_PIO_OER = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
+ PWM_PIO_PDR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
PWM_PIO_ABSR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
PMC_PCER |= BV(PWMC_ID);
/*
* Set pwm mode:
* - set period alidned to left
- * - set output waveform to low level
+ * - set output waveform to start at high level
* - allow duty cycle modify at next period event
*/
for (int ch = 0; ch < PWM_CNT; ch++)
+ {
*pwm_map[ch].mode_reg = 0;
+ *pwm_map[ch].mode_reg = BV(PWM_CPOL);
+ }
+
}