US0_IDR = 0xFFFFFFFF;
/* Set the vector. */
AIC_SVR(US0_ID) = uart0_irq_dispatcher;
- /* Initialize to edge triggered with defined priority. */
- AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
+ /* Initialize to level sensitive with defined priority. */
+ AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | SERIRQ_PRIORITY;
PMC_PCER = BV(US0_ID);
/*
US1_IDR = 0xFFFFFFFF;
/* Set the vector. */
AIC_SVR(US1_ID) = uart1_irq_dispatcher;
- /* Initialize to edge triggered with defined priority. */
- AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
+ /* Initialize to level sensitive with defined priority. */
+ AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | SERIRQ_PRIORITY;
PMC_PCER = BV(US1_ID);
/*
/* Should be read before US_CRS */
ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+ US0_CR = BV(US_RSTSTA);
char c = US0_RHR;
struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
/* Should be read before US_CRS */
ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+ US1_CR = BV(US_RSTSTA);
char c = US1_RHR;
struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;