* \author Daniele Basile <asterix@develer.com>
*/
+#include "hw/hw_ser.h" /* Required for bus macros overrides */
+#include "hw/hw_cpu.h" /* CLOCK_FREQ */
+
+#include "cfg/cfg_ser.h"
+#include <cfg/debug.h>
+
+
#include <io/arm.h>
#include <cpu/attr.h>
+
#include <drv/ser.h>
#include <drv/ser_p.h>
-#include <hw/hw_ser.h> /* Required for bus macros overrides */
-#include <hw/hw_cpu.h> /* CLOCK_FREQ */
-
#include <mware/fifobuf.h>
-#include <cfg/debug.h>
-#include <appconfig.h>
#define SERIRQ_PRIORITY 4 ///< default priority for serial irqs.
/* Should be read before US_CRS */
ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+ US0_CR = BV(US_RSTSTA);
char c = US0_RHR;
struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
/* Should be read before US_CRS */
ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+ US1_CR = BV(US_RSTSTA);
char c = US1_RHR;
struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;