Refactor parser.

[bertos.git] / bertos / cpu / arm / hw / crtat91sam7_rom.S

diff --git a/bertos/cpu/arm/hw/crtat91sam7_rom.S b/bertos/cpu/arm/hw/crtat91sam7_rom.S
index 0597f4a826c7f5b668e9b1e5a6661bfbb012fd28..51635fde4cb36b16a6ff32297bfea069d8989182 100644 (file)
--- a/bertos/cpu/arm/hw/crtat91sam7_rom.S
+++ b/bertos/cpu/arm/hw/crtat91sam7_rom.S
@@ -30,7 +30,6 @@
  *
  * -->
  *
- * \version $Id: $
  *
  * \author Francesco Sacchi <batt@develer.com>
  *
@@ -74,27 +73,26 @@
 #include "cfg/cfg_arch.h"
 
 
-#if CPU_FREQ != 48023000L
+#if CPU_FREQ != 48054857L
        /* Avoid errors on nightly test */
        #if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
-               #warning Clock registers set for 48.023MHz operation, revise following code if you want a different clock.
+               #warning Clock registers set for 48.055MHz operation, revise following code if you want a different clock.
        #endif
 #endif
 
 
 #if CPU_ARM_SAM7S_LARGE || CPU_ARM_SAM7X
-       /**
-       * With a 18.420MHz cristal, master clock is:
-       * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
-       */
+       /*
+        * With a 18.432MHz cristal, master clock is:
+        * (((18.432 * (PLL_MUL_VAL + 1)) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.055MHz
+        */
        #define PLL_MUL_VAL  72  /**< Real multiplier value is PLL_MUL_VAL + 1! */
        #define PLL_DIV_VAL  14
        #define AT91MCK_PRES PMC_PRES_CLK_2
 
-       /**
-       * Register I/O adresses.
-       * \{
-       */
+       /*
+        * Register I/O adresses.
+        */
        #define MC_BASE             0xFFFFFF00
        #define MC_FMR_OFF          0x00000060
        #define MC_FWS_2R3W         0x00000100
@@ -124,7 +122,7 @@
        #elif CPU_ARM_SAM7X
                #define PMC_PIO_CLK_EN ((1 << 2) | (1 << 3))
        #else
-               #error CPU non supported
+               #error CPU not supported
        #endif
 
        #define CKGR_MOR_OFF        0x00000020
@@ -137,11 +135,13 @@
        #define RSTC_KEY            0xA5000000
        #define RSTC_URSTEN           (1 << 0)
 
+       #define ARM_MODE_USR              0x10
        #define ARM_MODE_FIQ              0x11
        #define ARM_MODE_IRQ              0x12
        #define ARM_MODE_SVC              0x13
        #define ARM_MODE_ABORT            0x17
        #define ARM_MODE_UNDEF            0x1B
+       #define ARM_MODE_SYS              0x1F
 
 #else
        #error No register I/O definition for selected ARM CPU
@@ -353,7 +353,8 @@ _41:
         /*
          * Initialize user stack pointer.
          */
-        ldr     r13, =__stack_end
+       /* msr     CPSR_c, #ARM_MODE_SYS | 0xC0 */
+       ldr     r13, =__stack_end
 
 
        /*