*
*/
-#include "hw/hw_cpu.h"
#include <cpu/detect.h>
+#include "cfg/cfg_arch.h"
-#if CLOCK_FREQ != 48023000L
-#error Clock registers set for 48MHz operation, revise following code if you want a different clock.
+#if CPU_FREQ != 48023000L
+ /* Avoid errors on nightly test */
+ #if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
+ #warning Clock registers set for 48.023MHz operation, revise following code if you want a different clock.
+ #endif
#endif
-#if CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+#if CPU_ARM_SAM7S_LARGE || CPU_ARM_SAM7X
/**
* With a 18.420MHz cristal, master clock is:
* (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
#define WDT_WDDIS (1 << 15)
#define PMC_BASE 0xFFFFFC00
+ #define PMC_PCER_OFF 0x00000010
#define PMC_SR_OFF 0x00000068
#define PMC_MCKR_OFF 0x00000030
#define PMC_MOSCS (1 << 0)
#define PMC_PRES_MASK 0x0000001C
#define PMC_PRES_CLK_2 0x00000004
+ #if CPU_ARM_SAM7S_LARGE
+ #define PMC_PIO_CLK_EN (1 << 2)
+ #elif CPU_ARM_SAM7X
+ #define PMC_PIO_CLK_EN ((1 << 2) | (1 << 3))
+ #else
+ #error CPU not supported
+ #endif
+
#define CKGR_MOR_OFF 0x00000020
#define CKGR_PLLR_OFF 0x0000002C
#define CKGR_MOSCEN (1 << 0)
*/
ldr r13, =__stack_end
+
+ /*
+ * Enable clock for PIO(s)
+ */
+ ldr r1, =PMC_BASE
+ mov r0, #PMC_PIO_CLK_EN
+ str r0, [r1, #PMC_PCER_OFF]
+
+
/*
* Jump to main
*/