Better detection of concurrent ADC access.

[bertos.git] / bertos / cpu / arm / hw / crtat91sam7_rom.S

diff --git a/bertos/cpu/arm/hw/crtat91sam7_rom.S b/bertos/cpu/arm/hw/crtat91sam7_rom.S
index 0857795b2556ba4dc977cff198d78c24b98f33b3..a73b70d58ad9ff51386606d112fa1154c82b1787 100644 (file)
--- a/bertos/cpu/arm/hw/crtat91sam7_rom.S
+++ b/bertos/cpu/arm/hw/crtat91sam7_rom.S
@@ -70,20 +70,19 @@
  *
  */
 
-#include "hw/hw_cpu.h"
 #include <cpu/detect.h>
 #include "cfg/cfg_arch.h"
 
 
-#if CLOCK_FREQ != 48023000L
+#if CPU_FREQ != 48023000L
        /* Avoid errors on nightly test */
        #if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
-               #error Clock registers set for 48MHz operation, revise following code if you want a different clock.
+               #warning Clock registers set for 48.023MHz operation, revise following code if you want a different clock.
        #endif
 #endif
 
 
-#if CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+#if CPU_ARM_SAM7S_LARGE || CPU_ARM_SAM7X
        /**
        * With a 18.420MHz cristal, master clock is:
        * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
@@ -109,6 +108,7 @@
        #define WDT_WDDIS            (1 << 15)
 
        #define PMC_BASE            0xFFFFFC00
+       #define PMC_PCER_OFF        0x00000010
        #define PMC_SR_OFF          0x00000068
        #define PMC_MCKR_OFF        0x00000030
        #define PMC_MOSCS             (1 << 0)
@@ -119,6 +119,14 @@
        #define PMC_PRES_MASK       0x0000001C
        #define PMC_PRES_CLK_2      0x00000004
 
+       #if CPU_ARM_SAM7S_LARGE
+               #define PMC_PIO_CLK_EN (1 << 2)
+       #elif CPU_ARM_SAM7X
+               #define PMC_PIO_CLK_EN ((1 << 2) | (1 << 3))
+       #else
+               #error CPU not supported
+       #endif
+
        #define CKGR_MOR_OFF        0x00000020
        #define CKGR_PLLR_OFF       0x0000002C
        #define CKGR_MOSCEN           (1 << 0)
@@ -347,6 +355,15 @@ _41:
          */
         ldr     r13, =__stack_end
 
+
+       /*
+        * Enable clock for PIO(s)
+        */
+        ldr     r1, =PMC_BASE
+        mov     r0, #PMC_PIO_CLK_EN
+        str     r0, [r1, #PMC_PCER_OFF]
+
+
         /*
          * Jump to main
          */