#include <io/arm.h>
#include <cfg/macros.h>
+#include "cfg/cfg_wdt.h"
+
#define USE_FIXED_PLL 1
-#define XTAL_FREQ 18420000UL
+#define XTAL_FREQ 18432000UL
#if USE_FIXED_PLL
- #if CPU_FREQ != 48023000L
+ #if CPU_FREQ != 48054857L
/* Avoid errors on nightly test */
#if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
- #warning Clock registers set for 48.023MHz operation, revise following code if you want a different clock.
+ #warning Clock registers set for 48.055MHz operation, revise following code if you want a different clock.
#endif
#endif
/*
- * With a 18.420MHz cristal, master clock is:
- * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
+ * With a 18.432MHz cristal, master clock is:
+ * (((18.432 * (PLL_MUL_VAL + 1)) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.055MHz
*/
#define PLL_MUL_VAL 72 /**< Real multiplier value is PLL_MUL_VAL + 1! */
#define PLL_DIV_VAL 14
*/
void __init1(void)
{
+ /*
+ * Compute number of master clock cycles in 1.5us.
+ * Needed by flash writing functions.
+ * The maximum FMCN value is 0xFF and 0 can be used only if
+ * master clock is less than 33kHz.
+ */
+ #define MCN DIV_ROUNDUP(CPU_FREQ, 666667UL)
+ #define FMCN (CPU_FREQ <= 33333UL ? 0 : (MCN < 0xFF ? MCN : 0xFF))
+
+ #if CPU_FREQ < 30000000UL
+ /* Use 1 cycles for flash access. */
+ MC_FMR = FMCN << MC_FMCN_SHIFT | MC_FWS_1R2W;
+ #else
+ /* Use 2 cycles for flash access. */
+ MC_FMR = FMCN << MC_FMCN_SHIFT | MC_FWS_2R3W;
+ #endif
+
/* Disable all interrupts. Useful for debugging w/o target reset. */
AIC_EOICR = 0xFFFFFFFF;
AIC_IDCR = 0xFFFFFFFF;
- /* The watchdog is enabled after processor reset. Disable it. */
- WDT_MR = BV(WDT_WDDIS);
+ #if CONFIG_WATCHDOG == 0
+ /* The watchdog is enabled after processor reset. Disable it. */
+ WDT_MR = BV(WDT_WDDIS);
+ #endif
/*
* Enable the main oscillator. Set startup time of 6 * 8 slow