#define USE_FIXED_PLL 1
-#define XTAL_FREQ 18420000UL
+#define XTAL_FREQ 18432000UL
#if USE_FIXED_PLL
- #if CPU_FREQ != 48023000L
+ #if CPU_FREQ != 48054857L
/* Avoid errors on nightly test */
#if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
- #warning Clock registers set for 48.023MHz operation, revise following code if you want a different clock.
+ #warning Clock registers set for 48.055MHz operation, revise following code if you want a different clock.
#endif
#endif
/*
- * With a 18.420MHz cristal, master clock is:
- * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
+ * With a 18.432MHz cristal, master clock is:
+ * (((18.432 * (PLL_MUL_VAL + 1)) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.055MHz
*/
#define PLL_MUL_VAL 72 /**< Real multiplier value is PLL_MUL_VAL + 1! */
#define PLL_DIV_VAL 14