Add server tcp api.

[bertos.git] / bertos / cpu / arm / io / at91sam7.h

diff --git a/bertos/cpu/arm/io/at91sam7.h b/bertos/cpu/arm/io/at91sam7.h
index 2783307faf27bf130e85c351eb57687c5d582c42..6c645dcab9074958f9860044f8770453e9cc9558 100644 (file)
--- a/bertos/cpu/arm/io/at91sam7.h
+++ b/bertos/cpu/arm/io/at91sam7.h
@@ -30,7 +30,6 @@
  *
  * -->
  *
- * \version $Id$
  *
  * \author Francesco Sacchi <batt@develer.com>
  * \author Daniele Basile <asterix@develer.com>
@@ -144,13 +143,34 @@
 
 #endif
 
-#if CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256
+#if CPU_ARM_AT91SAM7S64
+       #define FLASH_MEM_SIZE          0x10000UL ///< Internal flash memory size
+       #define FLASH_PAGE_SIZE_BYTES         128 ///< Size of cpu flash memory page in bytes
+       #define FLASH_BANKS_NUM                 1 ///< Number of flash banks
+       #define FLASH_SECTORS_NUM              16 ///< Number of flash sector
+       #define FLASH_PAGE_PER_SECTOR          32 ///< Number of page for sector
+
+#elif CPU_ARM_AT91SAM7S128 || CPU_ARM_AT91SAM7X128
+       #define FLASH_MEM_SIZE          0x20000UL ///< Internal flash memory size
+       #define FLASH_PAGE_SIZE_BYTES         256 ///< Size of cpu flash memory page in bytes
+       #define FLASH_BANKS_NUM                 1 ///< Number of flash banks
+       #define FLASH_SECTORS_NUM               8 ///< Number of flash sector
+       #define FLASH_PAGE_PER_SECTOR          64 ///< Number of page for sector
+
+#elif CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256
        #define FLASH_MEM_SIZE          0x40000UL ///< Internal flash memory size
        #define FLASH_PAGE_SIZE_BYTES         256 ///< Size of cpu flash memory page in bytes
        #define FLASH_BANKS_NUM                 1 ///< Number of flash banks
        #define FLASH_SECTORS_NUM              16 ///< Number of flash sector
        #define FLASH_PAGE_PER_SECTOR          64 ///< Number of page for sector
 
+#elif CPU_ARM_AT91SAM7S512 || CPU_ARM_AT91SAM7X512
+       #define FLASH_MEM_SIZE          0x80000UL ///< Internal flash memory size
+       #define FLASH_PAGE_SIZE_BYTES         256 ///< Size of cpu flash memory page in bytes
+       #define FLASH_BANKS_NUM                 2 ///< Number of flash banks
+       #define FLASH_SECTORS_NUM              32 ///< Number of flash sector
+       #define FLASH_PAGE_PER_SECTOR          64 ///< Number of page for sector
+
 #else
        #error Memory size definition for selected ARM CPU
 #endif
@@ -170,6 +190,7 @@
 #include "at91_spi.h"
 #include "at91_twi.h"
 #include "at91_ssc.h"
+#include "at91_emac.h"
 //TODO: add other peripherals
 
 /**
@@ -348,6 +369,7 @@
        #define PWM_PIO_PDR     PIOB_PDR
        #define PWM_PIO_PER     PIOB_PER
        #define PWM_PIO_CODR    PIOB_CODR
+       #define PWM_PIO_SODR    PIOB_SODR
        #define PWM_PIO_OER     PIOB_OER
        #define PWM_PIO_ABSR    PIOB_ASR
 
@@ -360,6 +382,7 @@
        #define PWM_PIO_PDR     PIOA_PDR
        #define PWM_PIO_PER     PIOA_PER
        #define PWM_PIO_CODR    PIOA_CODR
+       #define PWM_PIO_SODR    PIOA_SODR
        #define PWM_PIO_OER     PIOA_OER
        #define PWM_PIO_ABSR    PIOA_BSR
 
@@ -409,4 +432,54 @@
 #endif
 /*\}*/
 
+
+/**
+ * Pin definition MII/RMII PHY interdace
+ */
+#if CPU_ARM_SAM7X
+       #define PHY_TXCLK_BIT      BV(0)
+       #define PHY_TXEN_BIT       BV(1)
+       #define PHY_TXD0_BIT       BV(2)
+       #define PHY_TXD1_BIT       BV(3)
+       #define PHY_CRS_BIT        BV(4)
+       #define PHY_RXD0_BIT       BV(5)
+       #define PHY_RXD1_BIT       BV(6)
+       #define PHY_RXER_BIT       BV(7)
+       #define PHY_MDC_BIT        BV(8)
+       #define PHY_MDIO_BIT       BV(9)
+       #define PHY_TXD2_BIT       BV(10)
+       #define PHY_TXD3_BIT       BV(11)
+       #define PHY_TXER_BIT       BV(12)
+       #define PHY_RXD2_BIT       BV(13)
+       #define PHY_RXD3_BIT       BV(14)
+       #define PHY_RXDV_BIT       BV(15)
+       #define PHY_COL_BIT        BV(16)
+       #define PHY_RXCLK_BIT      BV(17)
+
+#elif CPU_ARM_SAM7S_LARGE
+       /* No ethernet interface is present on this cpu */
+#else
+       #error No MII/RMII PHY pins interface was define for select CPU.
+#endif
+
+#define PHY_MII_PINS   \
+       ( PHY_TXEN_BIT \
+       | PHY_TXD0_BIT \
+       | PHY_TXD1_BIT \
+       | PHY_CRS_BIT \
+       | PHY_RXD0_BIT \
+       | PHY_RXD1_BIT \
+       | PHY_RXER_BIT \
+       | PHY_MDC_BIT \
+       | PHY_MDIO_BIT \
+       | PHY_TXD2_BIT \
+       | PHY_TXD3_BIT \
+       | PHY_TXER_BIT \
+       | PHY_RXD2_BIT \
+       | PHY_RXD3_BIT \
+       | PHY_RXDV_BIT \
+       | PHY_COL_BIT \
+       | PHY_RXCLK_BIT)
+// \}
+
 #endif /* AT91SAM7_H */