add support to the IAR Embedded Workbench(TM) compiler
[bertos.git] / bertos / cpu / attr.h
index 5f5217f03ca3ac3297085411368d95246dd34ef5..5c2107a8b93fea8ad45f29efccca9a0ac42d031b 100644 (file)
                #define CPU_RAM_START 0x20000000
        #endif
 
-       #if defined(__ARMEB__)
-               #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
-       #elif defined(__ARMEL__)
-               #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
-       #else
-               #error Unable to detect Cortex-M3 endianess!
-       #endif
+    #if defined( __ICCARM__)
+        #if ((defined __LITTLE_ENDIAN__) && (__LITTLE_ENDIAN__ == 0))
+            #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+        #elif ((defined __LITTLE_ENDIAN__) && (__LITTLE_ENDIAN__ == 1))
+                   #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+        #else
+            #error Unable to detect Cortex-M3 endianess!
+        #endif
+
+       #define NOP            __no_operation()
+    #else
+        #if defined(__ARMEB__) // GCC
+            #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+        #elif defined(__ARMEL__) // GCC
+            #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+        #else
+            #error Unable to detect Cortex-M3 endianess!
+        #endif
 
        #define NOP         asm volatile ("nop")
        #define PAUSE       asm volatile ("wfi" ::: "memory")
         * Function attribute to move it into ram memory.
         */
        #define RAM_FUNC __attribute__((section(".ramfunc")))
+    #endif
 
 #elif CPU_PPC
 
 
 #ifndef PAUSE
        /// Generic PAUSE implementation.
-       #define PAUSE   {NOP; MEMORY_BARRIER;}
+       #define PAUSE   do {NOP; MEMORY_BARRIER;} while (0)
 #endif
 
 #endif /* CPU_ATTR_H */