sam3: add register definitions for RSTC and EMAC

[bertos.git] / bertos / cpu / attr.h

diff --git a/bertos/cpu/attr.h b/bertos/cpu/attr.h
index 33901d06539b3f580a63e88c49e1d00eae98fc88..5f5217f03ca3ac3297085411368d95246dd34ef5 100644 (file)
--- a/bertos/cpu/attr.h
+++ b/bertos/cpu/attr.h
@@ -144,7 +144,7 @@
                         * to get them transparently copied to SRAM for zero-wait-state
                         * operation.
                         */
-                       #define FAST_FUNC __attribute__((section(".data")))
+                       #define FAST_FUNC __attribute__((section(".ramfunc")))
 
                        /**
                         * Data attribute to move constant data to fast memory storage.
@@ -161,7 +161,7 @@
                /*
                 * Function attribute to move it into ram memory.
                 */
-               #define RAM_FUNC __attribute__((section(".data")))
+               #define RAM_FUNC __attribute__((section(".ramfunc")))
 
        #endif /* !__IAR_SYSTEMS_ICC_ */
 #elif CPU_CM3
@@ -171,11 +171,11 @@
        #define CPU_HARVARD            0
 
        /// Valid pointers should be >= than this value (used for debug)
-       #if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32F103RB)
+       #if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32 || CPU_CM3_SAM3)
                #define CPU_RAM_START 0x20000000
        #else
-               #warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x200
-               #define CPU_RAM_START 0x200
+               #warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x20000000
+               #define CPU_RAM_START 0x20000000
        #endif
 
        #if defined(__ARMEB__)
@@ -190,6 +190,11 @@
        #define PAUSE       asm volatile ("wfi" ::: "memory")
        #define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
 
+       /*
+        * Function attribute to move it into ram memory.
+        */
+       #define RAM_FUNC __attribute__((section(".ramfunc")))
+
 #elif CPU_PPC
 
        #define CPU_REG_BITS           (CPU_PPC32 ? 32 : 64)
@@ -210,7 +215,7 @@
        #define CPU_REG_BITS            16
        #define CPU_REGS_CNT            FIXME
        #define CPU_BYTE_ORDER          CPU_BIG_ENDIAN
-       #define CPU_HARVARD             1
+       #define CPU_HARVARD             1
 
        /* Memory is word-addessed in the DSP56K */
        #define CPU_BITS_PER_CHAR  16
@@ -239,7 +244,7 @@
                #define CPU_RAM_START       0x60
        #elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
                #define CPU_RAM_START       0x100
-       #elif CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
+       #elif CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
                #define CPU_RAM_START       0x200
        #else
                #warning Fix CPU_RAM_START address for your AVR, default value set to 0x100
@@ -254,7 +259,7 @@
        #define CPU_HARVARD                     0
 
        /// Valid pointers should be >= than this value (used for debug)
-       #define CPU_RAM_START               0x200
+       #define CPU_RAM_START           0x200
 
        #define NOP                     __asm__ __volatile__ ("nop")