DIV_ROUNDUP: new macro.

[bertos.git] / bertos / cpu / attr.h

diff --git a/bertos/cpu/attr.h b/bertos/cpu/attr.h
index 5e24fa3c9d3ee7b57ae6d19ad36212f2798789a5..a317f1e810f1d9d86243df4a33efaf0a0f0d88fb 100644 (file)
--- a/bertos/cpu/attr.h
+++ b/bertos/cpu/attr.h
@@ -109,6 +109,8 @@
        /// Valid pointers should be >= than this value (used for debug)
        #if CPU_ARM_AT91
                #define CPU_RAM_START           0x00200000
+       #elif CPU_ARM_LPC2
+               #define CPU_RAM_START           0x40000000
        #else
                #warning Fix CPU_RAM_START address for your ARM, default value set to 0x200
                #define CPU_RAM_START           0x200
@@ -165,7 +167,7 @@
 #elif CPU_CM3
 
        #define CPU_REG_BITS           32
-       #define CPU_REGS_CNT           fixme
+       #define CPU_REGS_CNT           16
        #define CPU_HARVARD            0
 
        /// Valid pointers should be >= than this value (used for debug)
@@ -181,12 +183,28 @@
        #elif defined(__ARMEL__)
                #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
        #else
-               #error Unable to detect Cortex-M3 endianness!
+               #error Unable to detect Cortex-M3 endianess!
        #endif
 
-       #define NOP         fixme
+       #define NOP         asm volatile ("nop")
+       #define PAUSE       asm volatile ("wfi" ::: "memory")
        #define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
 
+       /*
+        * FIXME: builtin GCC memset() can be buggy! We need to redefine it
+        * here for this architecture. :(
+        */
+       #include <cfg/compiler.h>
+       #define memset  __cm3_memset
+       INLINE void *__cm3_memset(void *s, int c, size_t n)
+       {
+               uint8_t *p = (uint8_t *)s;
+
+               while (n--)
+                       *p++ = c;
+               return s;
+       }
+
 #elif CPU_PPC
 
        #define CPU_REG_BITS           (CPU_PPC32 ? 32 : 64)