* \brief CPU-specific attributes.
*
* \author Giovanni Bajo <rasky@develer.com>
- * \author Bernardo Innocenti <bernie@develer.com>
+ * \author Bernie Innocenti <bernie@codewiz.org>
* \author Stefano Fedrigo <aleph@develer.com>
* \author Francesco Sacchi <batt@develer.com>
*/
#include "detect.h"
-#include <cfg/cfg_attr.h> /* CONFIG_FAST_MEM */
+#include "cfg/cfg_attr.h" /* CONFIG_FAST_MEM */
+#include "cfg/cfg_arch.h" /* ARCH_EMUL */
#include <cfg/compiler.h> /* for uintXX_t */
-#include <cfg/cfg_arch.h> /* ARCH_EMUL */
/**
#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
#define CPU_HARVARD 0
+ /// Valid pointers should be >= than this value (used for debug)
+ #define CPU_RAM_START 0x100
+
#elif CPU_X86
#define NOP asm volatile ("nop")
#define CPU_REG_BITS 32
#endif
+ /// Valid pointers should be >= than this value (used for debug)
+ #define CPU_RAM_START 0x1000
+
#elif CPU_ARM
/* Register counts include SREG too */
#define CPU_SP_ON_EMPTY_SLOT 0
#define CPU_HARVARD 0
+ /// Valid pointers should be >= than this value (used for debug)
+ #define CPU_RAM_START 0x200
+
#ifdef __IAR_SYSTEMS_ICC__
#warning Check CPU_BYTE_ORDER
#define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
#else /* GCC and compatibles */
#if defined(__ARMEB__)
- #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
- #elif defined(__ARMEL__)
- #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+ #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+ #elif defined(__ARMEL__)
+ #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
#else
#error Unable to detect ARM endianness!
#endif
#define NOP asm volatile ("mov r0,r0" ::)
/**
- * Initialization value for registers in stack frame.
- * The register index is not directly corrispondent to CPU
- * register numbers, but is related to how are pushed to
- * stack (\see asm_switch_context).
+ * Initialization value for registers in stack frame.
+ * The register index is not directly corrispondent to CPU
+ * register numbers, but is related to how are pushed to
+ * stack (\see asm_switch_context).
* Index (CPU_SAVED_REGS_CNT - 1) is the CPSR register,
* the initial value is set to:
* - All flags (N, Z, C, V) set to 0.
* - IRQ and FIQ enabled.
* - ARM state.
* - CPU in Supervisor Mode (SVC).
- */
+ */
#define CPU_REG_INIT_VALUE(reg) (reg == (CPU_SAVED_REGS_CNT - 1) ? 0x13 : 0)
#if CONFIG_FAST_MEM
/* Register counts include SREG too */
#define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
#define CPU_REGS_CNT FIXME
- #define CPU_SAVED_REGS_CNT FIXME
+ #define CPU_SAVED_REGS_CNT 1 // FIXME
#define CPU_STACK_GROWS_UPWARD 0 //FIXME
#define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
#define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
#define CPU_HARVARD 0
+ /// Valid pointers should be >= than this value (used for debug)
+ #define CPU_RAM_START 0x1000
+
#elif CPU_DSP56K
#define NOP asm(nop)
#define SIZEOF_LONG 2
#define SIZEOF_PTR 1
+ /// Valid pointers should be >= than this value (used for debug)
+ #define CPU_RAM_START 0x200
+
#elif CPU_AVR
#define NOP asm volatile ("nop" ::)
*/
#define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
+ /// Valid pointers should be >= than this value (used for debug)
+ #define CPU_RAM_START 0x100
+
#else
#error No CPU_... defined.
#endif
#elif CPU_AVR
/*
- * In AVR, the addresses are pushed into the stack as little-endian, while
+ * On AVR, addresses are pushed into the stack as little-endian, while
* memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
* no natural endianess).
*/