* to get them transparently copied to SRAM for zero-wait-state
* operation.
*/
- #define FAST_FUNC __attribute__((section(".data")))
+ #define FAST_FUNC __attribute__((section(".ramfunc")))
/**
* Data attribute to move constant data to fast memory storage.
/*
* Function attribute to move it into ram memory.
*/
- #define RAM_FUNC __attribute__((section(".data")))
+ #define RAM_FUNC __attribute__((section(".ramfunc")))
#endif /* !__IAR_SYSTEMS_ICC_ */
#elif CPU_CM3
#define CPU_RAM_START 0x20000000
#endif
- #if defined(__ARMEB__)
- #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
- #elif defined(__ARMEL__)
- #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
- #else
- #error Unable to detect Cortex-M3 endianess!
- #endif
+ #if defined( __ICCARM__)
+ #if ((defined __LITTLE_ENDIAN__) && (__LITTLE_ENDIAN__ == 0))
+ #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+ #elif ((defined __LITTLE_ENDIAN__) && (__LITTLE_ENDIAN__ == 1))
+ #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+ #else
+ #error Unable to detect Cortex-M3 endianess!
+ #endif
+
+ #define NOP __no_operation()
+ #else
+ #if defined(__ARMEB__) // GCC
+ #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+ #elif defined(__ARMEL__) // GCC
+ #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+ #else
+ #error Unable to detect Cortex-M3 endianess!
+ #endif
#define NOP asm volatile ("nop")
#define PAUSE asm volatile ("wfi" ::: "memory")
/*
* Function attribute to move it into ram memory.
*/
- #define RAM_FUNC __attribute__((section(".data")))
+ #define RAM_FUNC __attribute__((section(".ramfunc")))
+ #endif
#elif CPU_PPC
#define CPU_RAM_START 0x100
#elif CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define CPU_RAM_START 0x200
+ #elif CPU_AVR_XMEGA_D
+ #define CPU_RAM_START 0x2000
#else
#warning Fix CPU_RAM_START address for your AVR, default value set to 0x100
#define CPU_RAM_START 0x100
#ifndef PAUSE
/// Generic PAUSE implementation.
- #define PAUSE {NOP; MEMORY_BARRIER;}
+ #define PAUSE do {NOP; MEMORY_BARRIER;} while (0)
#endif
#endif /* CPU_ATTR_H */