Reformat.

[bertos.git] / bertos / cpu / attr.h

diff --git a/bertos/cpu/attr.h b/bertos/cpu/attr.h
index 4090abb9411bf38e7a6eedb925632174b064543c..f2183faaa7f7b8bebff271cb5b73b7caca7aba66 100644 (file)
--- a/bertos/cpu/attr.h
+++ b/bertos/cpu/attr.h
@@ -42,10 +42,11 @@
 #define CPU_ATTR_H
 
 #include "detect.h"
-#include <cfg/compiler.h> /* for uintXX_t */
-#include <cfg/arch_config.h>  /* ARCH_EMUL */
 
-#include "appconfig.h" // CONFIG_FAST_MEM
+#include "cfg/cfg_attr.h"      /* CONFIG_FAST_MEM */
+#include "cfg/cfg_arch.h"      /* ARCH_EMUL */
+#include <cfg/compiler.h>      /* for uintXX_t */
+
 
 /**
  * \name Macros for determining CPU endianness.
@@ -114,9 +115,9 @@
        #else /* GCC and compatibles */
 
                #if defined(__ARMEB__)
-                       #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
-               #elif defined(__ARMEL__)
-                       #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+                       #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+               #elif defined(__ARMEL__)
+                       #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
                #else
                        #error Unable to detect ARM endianness!
                #endif
@@ -124,17 +125,17 @@
                #define NOP            asm volatile ("mov r0,r0" ::)
 
                /**
-                * Initialization value for registers in stack frame.
-                * The register index is not directly corrispondent to CPU
-                * register numbers, but is related to how are pushed to
-                * stack (\see asm_switch_context).
+                * Initialization value for registers in stack frame.
+                * The register index is not directly corrispondent to CPU
+                * register numbers, but is related to how are pushed to
+                * stack (\see asm_switch_context).
                 * Index (CPU_SAVED_REGS_CNT - 1) is the CPSR register,
                 * the initial value is set to:
                 * - All flags (N, Z, C, V) set to 0.
                 * - IRQ and FIQ enabled.
                 * - ARM state.
                 * - CPU in Supervisor Mode (SVC).
-                */
+                */
                #define CPU_REG_INIT_VALUE(reg) (reg == (CPU_SAVED_REGS_CNT - 1) ? 0x13 : 0)
 
                #if CONFIG_FAST_MEM
@@ -219,19 +220,6 @@
         */
        #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
 
-       #warning FIXME:This macro are empty for AVR target, implent it!
-       /**
-        * Function attribute for use with performance critical code.
-        */
-       #define FAST_FUNC /* */
-
-       /**
-        * Data attribute to move constant data to fast memory storage.
-        *
-        * \see FAST_FUNC
-        */
-       #define FAST_RODATA /* */
-
 #else
        #error No CPU_... defined.
 #endif
@@ -241,7 +229,6 @@
        #define CPU_REG_INIT_VALUE(reg)     0
 #endif
 
-
 #ifndef CPU_STACK_GROWS_UPWARD
        #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
 #endif
@@ -250,6 +237,20 @@
        #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
 #endif
 
+#ifndef FAST_FUNC
+       /**
+        * Function attribute for use with performance critical code.
+        */
+       #define FAST_FUNC /* */
+#endif
+
+#ifndef FAST_RODATA
+       /**
+        * Data attribute to move constant data to fast memory storage.
+        */
+       #define FAST_RODATA /* */
+#endif
+
 /*
  * Support stack handling peculiarities of a few CPUs.
  *