*
* \brief ADC hardware-specific definition
*
- * \version $Id$
* \author Francesco Sacchi <batt@develer.com>
*
* This module is automatically included so no need to include
*/
ISR(ADC_vect)
{
- sig_signal(adc_process, SIG_ADC_COMPLETE);
+ sig_post(adc_process, SIG_ADC_COMPLETE);
}
#endif /* CONFIG_KERN */
* Select mux channel \a ch.
* \todo only first 8 channels are selectable!
*/
-INLINE void adc_hw_select_ch(uint8_t ch)
+void adc_hw_select_ch(uint8_t ch)
{
/* Set to 0 all mux registers */
- ADMUX &= ~(BV(MUX4) | BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
+ #if CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA168
+ ADMUX &= ~(BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
+ #elif CPU_AVR_ATMEGA32 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
+ ADMUX &= ~(BV(MUX4) | BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
+ #else
+ #error Unknown CPU
+ #endif
/* Select channel, only first 8 channel modes are supported for now */
ADMUX |= (ch & 0x07);
* If a kernel is present, preempt until convertion is complete, otherwise
* a busy wait on ADCS bit is done.
*/
-INLINE uint16_t adc_hw_read(void)
+uint16_t adc_hw_read(void)
{
// Ensure another convertion is not running.
ASSERT(!(ADCSRA & BV(ADSC)));
/**
* Init ADC hardware.
*/
-INLINE void adc_hw_init(void)
+void adc_hw_init(void)
{
/*
* Select channel 0 as default,