sam3n: update clock and kdebug modules to use lastest register definion convention
[bertos.git] / bertos / cpu / avr / drv / adc_avr.c
index 20aa2a192de4144c4c1634516d9f7f2ebf8a9da1..c42f8e3ba4f9c6ae67db243790e8542f38883575 100644 (file)
@@ -31,7 +31,6 @@
  *
  * \brief ADC hardware-specific definition
  *
- * \version $Id$
  * \author Francesco Sacchi <batt@develer.com>
  *
  * This module is automatically included so no need to include
@@ -89,7 +88,7 @@
         */
        ISR(ADC_vect)
        {
-               sig_signal(adc_process, SIG_ADC_COMPLETE);
+               sig_post(adc_process, SIG_ADC_COMPLETE);
        }
 #endif /* CONFIG_KERN */
 
 void adc_hw_select_ch(uint8_t ch)
 {
        /* Set to 0 all mux registers */
-       ADMUX &= ~(BV(MUX4) | BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
+       #if CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA168
+               ADMUX &= ~(BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
+       #elif CPU_AVR_ATMEGA32 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281 \
+             || CPU_AVR_ATMEGA1280
+               ADMUX &= ~(BV(MUX4) | BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
+               #if CPU_AVR_ATMEGA1280
+                       ADCSRB &= ~(BV(MUX5));
+               #endif
+       #else
+               #error Unknown CPU
+       #endif
 
-       /* Select channel, only first 8 channel modes are supported for now */
+       /* Select channel, only first 8 channel modes are supported */
        ADMUX |= (ch & 0x07);
+
+       #if CPU_AVR_ATMEGA1280
+               /* Select channel, all 16 channels are supported */
+               if (ch > 0x07)
+                       ADCSRB |= BV(MUX5);
+
+       #endif
+
 }