/*\}*/
#endif
-#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
+#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define BIT_RXCIE0 RXCIE0
#define BIT_RXEN0 RXEN0
#define BIT_TXEN0 TXEN0
#define BIT_RXEN1 RXEN1
#define BIT_TXEN1 TXEN1
#define BIT_UDRIE1 UDRIE1
- #if CPU_AVR_ATMEGA1280
+ #if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define BIT_RXCIE2 RXCIE2
#define BIT_RXEN2 RXEN2
#define BIT_TXEN2 TXEN2
/* SPI port and pin configuration */
#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281 \
- || CPU_AVR_ATMEGA1280
+ || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define SPI_PORT PORTB
#define SPI_DDR DDRB
#define SPI_SS_BIT PB0
#endif
/* USART register definitions */
-#if CPU_AVR_ATMEGA1280
+#if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define AVR_HAS_UART1 1
#define AVR_HAS_UART2 1
#define AVR_HAS_UART3 1