/*\}*/
#endif
-#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
+#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define BIT_RXCIE0 RXCIE0
#define BIT_RXEN0 RXEN0
#define BIT_TXEN0 TXEN0
#define BIT_RXEN1 RXEN1
#define BIT_TXEN1 TXEN1
#define BIT_UDRIE1 UDRIE1
- #if CPU_AVR_ATMEGA1280
+ #if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define BIT_RXCIE2 RXCIE2
#define BIT_RXEN2 RXEN2
#define BIT_TXEN2 TXEN2
/* SPI port and pin configuration */
#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281 \
- || CPU_AVR_ATMEGA1280
+ || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define SPI_PORT PORTB
#define SPI_DDR DDRB
#define SPI_SS_BIT PB0
#define SPI_SCK_BIT PB5
#define SPI_MOSI_BIT PB3
#define SPI_MISO_BIT PB4
+#elif CPU_AVR_ATMEGA32
+ #define SPI_PORT PORTB
+ #define SPI_DDR DDRB
+ #define SPI_SS_BIT PB4
+ #define SPI_SCK_BIT PB7
+ #define SPI_MOSI_BIT PB5
+ #define SPI_MISO_BIT PB6
#else
#error Unknown architecture
#endif
/* USART register definitions */
-#if CPU_AVR_ATMEGA1280
+#if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define AVR_HAS_UART1 1
#define AVR_HAS_UART2 1
#define AVR_HAS_UART3 1
#define USART0_UDRE_vect USART_UDRE_vect
#define USART0_RX_vect USART_RX_vect
#define USART0_TX_vect USART_TX_vect
-#elif CPU_AVR_ATMEGA8
+#elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32
#define AVR_HAS_UART1 0
#define AVR_HAS_UART2 0
#define AVR_HAS_UART3 0
#define UDR0 UDR
#define UBRR0L UBRRL
#define UBRR0H UBRRH
+ #define UPM01 UPM1
+ #define UPM00 UPM0
#define USART0_UDRE_vect USART_UDRE_vect
- #define USART0_RX_vect USART_RX_vect
- #define USART0_TX_vect USART_TX_vect
+ #define USART0_RX_vect USART_RXC_vect
+ #define USART0_TX_vect USART_TXC_vect
#elif CPU_AVR_ATMEGA103
#define AVR_HAS_UART1 0
#define AVR_HAS_UART2 0