Rename CLOCK_FREQ macro to CPU_FREQ: now clock frequency has to be set in the makefile.

[bertos.git] / bertos / cpu / avr / drv / ser_avr.c

diff --git a/bertos/cpu/avr/drv/ser_avr.c b/bertos/cpu/avr/drv/ser_avr.c
index c4d4994520929b070c1c777ae2ed9fcdf3fccf98..d3cc743d0d6ca0e32d7d492832bccfd301a509b5 100644 (file)
--- a/bertos/cpu/avr/drv/ser_avr.c
+++ b/bertos/cpu/avr/drv/ser_avr.c
@@ -40,7 +40,7 @@
  */
 
 #include "hw/hw_ser.h"  /* Required for bus macros overrides */
-#include "hw/hw_cpu.h"  /* CLOCK_FREQ */
+#include <hw/hw_cpufreq.h>  /* CPU_FREQ */
 
 #include "cfg/cfg_ser.h"
 
@@ -51,7 +51,7 @@
 #include <drv/ser_p.h>
 #include <drv/timer.h>
 
-#include <mware/fifobuf.h>
+#include <struct/fifobuf.h>
 
 #include <avr/io.h>
 
@@ -304,7 +304,7 @@
 
 
 /* From the high-level serial driver */
-extern struct Serial ser_handles[SER_CNT];
+extern struct Serial *ser_handles[SER_CNT];
 
 /* TX and RX buffers */
 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
@@ -340,20 +340,6 @@ struct AvrSerial
 };
 
 
-/*
- * These are to trick GCC into *not* using absolute addressing mode
- * when accessing ser_handles, which is very expensive.
- *
- * Accessing through these pointers generates much shorter
- * (and hopefully faster) code.
- */
-struct Serial *ser_uart0 = &ser_handles[SER_UART0];
-#if AVR_HAS_UART1
-struct Serial *ser_uart1 = &ser_handles[SER_UART1];
-#endif
-struct Serial *ser_spi = &ser_handles[SER_SPI];
-
-
 
 /*
  * Callbacks
@@ -391,7 +377,7 @@ static void uart0_enabletxirq(struct SerialHardware *_hw)
 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
 {
        /* Compute baud-rate period */
-       uint16_t period = DIV_ROUND(CLOCK_FREQ / 16UL, rate) - 1;
+       uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
 
 #if !CPU_AVR_ATMEGA103
        UBRR0H = (period) >> 8;
@@ -444,7 +430,7 @@ static void uart1_enabletxirq(struct SerialHardware *_hw)
 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
 {
        /* Compute baud-rate period */
-       uint16_t period = DIV_ROUND(CLOCK_FREQ / 16UL, rate) - 1;
+       uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
 
        UBRR1H = (period) >> 8;
        UBRR1L = (period);
@@ -547,14 +533,14 @@ static void spi_starttx(struct SerialHardware *_hw)
 {
        struct AvrSerial *hw = (struct AvrSerial *)_hw;
 
-       cpuflags_t flags;
+       cpu_flags_t flags;
        IRQ_SAVE_DISABLE(flags);
 
        /* Send data only if the SPI is not already transmitting */
-       if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
+       if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI]->txfifo))
        {
                hw->sending = true;
-               SPDR = fifo_pop(&ser_spi->txfifo);
+               SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
        }
 
        IRQ_RESTORE(flags);
@@ -678,7 +664,7 @@ struct SerialHardware *ser_hw_getdesc(int unit)
 SIGNAL(SIG_CTS)
 {
        // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
-       UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+       UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
        EIMSK &= ~EIMSKF_CTS;
 }
 
@@ -692,7 +678,7 @@ SIGNAL(USART0_UDRE_vect)
 {
        SER_STROBE_ON;
 
-       struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
+       struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
 
        if (fifo_isempty(txfifo))
        {
@@ -706,7 +692,7 @@ SIGNAL(USART0_UDRE_vect)
        {
                // Disable rx interrupt and tx, enable CTS interrupt
                // UNTESTED
-               UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
+               UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
                EIFR |= EIMSKF_CTS;
                EIMSK |= EIMSKF_CTS;
        }
@@ -740,14 +726,14 @@ SIGNAL(SIG_UART0_TRANS)
 {
        SER_STROBE_ON;
 
-       struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
+       struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
        if (fifo_isempty(txfifo))
        {
                SER_UART0_BUS_TXOFF;
                UARTDescs[SER_UART0].sending = false;
        }
        else
-               UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+               UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
 
        SER_STROBE_OFF;
 }
@@ -763,7 +749,7 @@ SIGNAL(USART1_UDRE_vect)
 {
        SER_STROBE_ON;
 
-       struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
+       struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
 
        if (fifo_isempty(txfifo))
        {
@@ -777,7 +763,7 @@ SIGNAL(USART1_UDRE_vect)
        {
                // Disable rx interrupt and tx, enable CTS interrupt
                // UNTESTED
-               UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
+               UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
                EIFR |= EIMSKF_CTS;
                EIMSK |= EIMSKF_CTS;
        }
@@ -797,18 +783,18 @@ SIGNAL(USART1_UDRE_vect)
  *
  * \sa port 0 TX complete handler.
  */
-SIGNAL(SIG_UART1_TRANS)
+SIGNAL(USART1_TX_vect)
 {
        SER_STROBE_ON;
 
-       struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
+       struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
        if (fifo_isempty(txfifo))
        {
                SER_UART1_BUS_TXOFF;
                UARTDescs[SER_UART1].sending = false;
        }
        else
-               UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+               UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
 
        SER_STROBE_OFF;
 }
@@ -841,17 +827,17 @@ SIGNAL(USART0_RX_vect)
        //IRQ_ENABLE;
 
        /* Should be read before UDR */
-       ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+       ser_handles[SER_UART0]->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
 
        /* To clear the RXC flag we must _always_ read the UDR even when we're
         * not going to accept the incoming data, otherwise a new interrupt
         * will occur once the handler terminates.
         */
        char c = UDR0;
-       struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
+       struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo;
 
        if (fifo_isfull(rxfifo))
-               ser_uart0->status |= SERRF_RXFIFOOVERRUN;
+               ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN;
        else
        {
                fifo_push(rxfifo, c);
@@ -891,17 +877,17 @@ SIGNAL(USART1_RX_vect)
        //IRQ_ENABLE;
 
        /* Should be read before UDR */
-       ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+       ser_handles[SER_UART1]->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
 
        /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
         * not going to accept the incoming data
         */
        char c = UDR1;
-       struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
+       struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo;
        //ASSERT_VALID_FIFO(rxfifo);
 
        if (UNLIKELY(fifo_isfull(rxfifo)))
-               ser_uart1->status |= SERRF_RXFIFOOVERRUN;
+               ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN;
        else
        {
                fifo_push(rxfifo, c);
@@ -928,17 +914,17 @@ SIGNAL(SIG_SPI)
        SER_STROBE_ON;
 
        /* Read incoming byte. */
-       if (!fifo_isfull(&ser_spi->rxfifo))
-               fifo_push(&ser_spi->rxfifo, SPDR);
+       if (!fifo_isfull(&ser_handles[SER_SPI]->rxfifo))
+               fifo_push(&ser_handles[SER_SPI]->rxfifo, SPDR);
        /*
         * FIXME
        else
-               ser_spi->status |= SERRF_RXFIFOOVERRUN;
+               ser_handles[SER_SPI]->status |= SERRF_RXFIFOOVERRUN;
        */
 
        /* Send */
-       if (!fifo_isempty(&ser_spi->txfifo))
-               SPDR = fifo_pop(&ser_spi->txfifo);
+       if (!fifo_isempty(&ser_handles[SER_SPI]->txfifo))
+               SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
        else
                UARTDescs[SER_SPI].sending = false;