*/
#include "hw/hw_ser.h" /* Required for bus macros overrides */
-#include "hw/hw_cpu.h" /* CLOCK_FREQ */
+#include <hw/hw_cpufreq.h> /* CPU_FREQ */
#include "cfg/cfg_ser.h"
static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
{
/* Compute baud-rate period */
- uint16_t period = DIV_ROUND(CLOCK_FREQ / 16UL, rate) - 1;
+ uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
#if !CPU_AVR_ATMEGA103
UBRR0H = (period) >> 8;
static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
{
/* Compute baud-rate period */
- uint16_t period = DIV_ROUND(CLOCK_FREQ / 16UL, rate) - 1;
+ uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
UBRR1H = (period) >> 8;
UBRR1L = (period);
SIGNAL(SIG_CTS)
{
// Re-enable UDR empty interrupt and TX, then disable CTS interrupt
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
EIMSK &= ~EIMSKF_CTS;
}
{
// Disable rx interrupt and tx, enable CTS interrupt
// UNTESTED
- UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
+ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
EIFR |= EIMSKF_CTS;
EIMSK |= EIMSKF_CTS;
}
UARTDescs[SER_UART0].sending = false;
}
else
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
SER_STROBE_OFF;
}
{
// Disable rx interrupt and tx, enable CTS interrupt
// UNTESTED
- UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
+ UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
EIFR |= EIMSKF_CTS;
EIMSK |= EIMSKF_CTS;
}
*
* \sa port 0 TX complete handler.
*/
-SIGNAL(SIG_UART1_TRANS)
+SIGNAL(USART1_TX_vect)
{
SER_STROBE_ON;
UARTDescs[SER_UART1].sending = false;
}
else
- UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+ UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
SER_STROBE_OFF;
}