Remove duplicate define. Put all phy chip specific defines in its

[bertos.git] / bertos / cpu / cortex-m3 / drv / clock_lm3s.c

diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.c b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
index 1c643b58c77cdc4599d729b64508e59b91333178..0c79f8780c60017a4ce2673896c303b236aa9fdb 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
@@ -35,10 +35,13 @@
  * \author Andrea Righi <arighi@develer.com>
  */
 
+#include "clock_lm3s.h"
+
 #include <cfg/compiler.h>
 #include <cfg/debug.h>
-#include "io/lm3s.h"
-#include "clock_lm3s.h"
+
+#include <io/lm3s.h>
+
 
 /* The PLL VCO frequency is 400 MHz */
 #define PLL_VCO        400000000UL
@@ -51,7 +54,7 @@
 /*
  * Very small delay: each loop takes 3 cycles.
  */
-void NAKED __delay(unsigned long iterations)
+void NAKED lm3s_busyWait(unsigned long iterations)
 {
        register uint32_t __n asm("r0") = iterations;
 
@@ -62,7 +65,7 @@ void NAKED __delay(unsigned long iterations)
                : : "r"(__n) : "memory", "cc");
 }
 
-unsigned long clock_get_rate(void)
+INLINE unsigned long clock_get_rate(void)
 {
        reg32_t rcc = HWREG(SYSCTL_RCC);
 
@@ -88,12 +91,33 @@ INLINE int evaluate_sysdiv(unsigned long freq)
        return i;
 }
 
-void clock_set_rate(void)
+void clock_init(void)
 {
        reg32_t rcc, rcc2;
        unsigned long clk;
        int i;
 
+       /*
+        * PLL may not function properly at default LDO setting.
+        *
+        * Description:
+        *
+        * In designs that enable and use the PLL module, unstable device
+        * behavior may occur with the LDO set at its default of 2.5 volts or
+        * below (minimum of 2.25 volts). Designs that do not use the PLL
+        * module are not affected.
+        *
+        * Workaround: Prior to enabling the PLL module, it is recommended that
+        * the default LDO voltage setting of 2.5 V be adjusted to 2.75 V using
+        * the LDO Power Control (LDOPCTL) register.
+        *
+        * Silicon Revision Affected: A1, A2
+        *
+        * See also: Stellaris LM3S1968 A2 Errata documentation.
+        */
+       if (REVISION_IS_A1 | REVISION_IS_A2)
+               HWREG(SYSCTL_LDOPCTL) = SYSCTL_LDOPCTL_2_75V;
+
        rcc = HWREG(SYSCTL_RCC);
        rcc2 = HWREG(SYSCTL_RCC2);
 
@@ -113,7 +137,7 @@ void clock_set_rate(void)
        HWREG(SYSCTL_RCC) = rcc;
        HWREG(SYSCTL_RCC) = rcc2;
 
-       __delay(16);
+       lm3s_busyWait(16);
 
        /*
         * Step #2: select the crystal value (XTAL) and oscillator source
@@ -139,7 +163,7 @@ void clock_set_rate(void)
         HWREG(SYSCTL_RCC) = rcc;
        HWREG(SYSCTL_RCC) = rcc2;
 
-       __delay(16);
+       lm3s_busyWait(16);
 
        /*
         * Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and
@@ -171,5 +195,5 @@ void clock_set_rate(void)
 
        HWREG(SYSCTL_RCC) = rcc;
 
-       __delay(16);
+       lm3s_busyWait(16);
 }