#include <cfg/compiler.h>
#include <cfg/debug.h>
-#include "io/lm3s.h"
+#include <io/lm3s.h>
#include "clock_lm3s.h"
/* The PLL VCO frequency is 400 MHz */
/*
* Very small delay: each loop takes 3 cycles.
*/
-INLINE void __delay(unsigned long iterations)
+void NAKED lm3s_busyWait(unsigned long iterations)
{
+ register uint32_t __n asm("r0") = iterations;
+
asm volatile (
- "1: subs %0, #1\n\t"
- " bne 1b\n\t"
- : "=r"(iterations) : : "memory", "cc");
+ "1: subs r0, #1\n\t"
+ "bne 1b\n\t"
+ "bx lr\n\t"
+ : : "r"(__n) : "memory", "cc");
}
-unsigned long clock_get_rate(void)
+INLINE unsigned long clock_get_rate(void)
{
reg32_t rcc = HWREG(SYSCTL_RCC);
return i;
}
-void clock_set_rate(void)
+void clock_init(void)
{
reg32_t rcc, rcc2;
unsigned long clk;
HWREG(SYSCTL_RCC) = rcc;
HWREG(SYSCTL_RCC) = rcc2;
+ lm3s_busyWait(16);
+
/*
* Step #2: select the crystal value (XTAL) and oscillator source
* (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL
HWREG(SYSCTL_RCC) = rcc;
HWREG(SYSCTL_RCC) = rcc2;
- __delay(16);
+ lm3s_busyWait(16);
/*
* Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and
HWREG(SYSCTL_RCC) = rcc;
- __delay(16);
+ lm3s_busyWait(16);
}