Silent warning.

[bertos.git] / bertos / cpu / cortex-m3 / drv / clock_lm3s.c

diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.c b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
index 1c643b58c77cdc4599d729b64508e59b91333178..0cd5da8415b9f555b7321fd7835bdb212195a99b 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
@@ -37,7 +37,7 @@
 
 #include <cfg/compiler.h>
 #include <cfg/debug.h>
-#include "io/lm3s.h"
+#include <io/lm3s.h>
 #include "clock_lm3s.h"
 
 /* The PLL VCO frequency is 400 MHz */
@@ -51,7 +51,7 @@
 /*
  * Very small delay: each loop takes 3 cycles.
  */
-void NAKED __delay(unsigned long iterations)
+void NAKED lm3s_busyWait(unsigned long iterations)
 {
        register uint32_t __n asm("r0") = iterations;
 
@@ -62,7 +62,7 @@ void NAKED __delay(unsigned long iterations)
                : : "r"(__n) : "memory", "cc");
 }
 
-unsigned long clock_get_rate(void)
+INLINE unsigned long clock_get_rate(void)
 {
        reg32_t rcc = HWREG(SYSCTL_RCC);
 
@@ -88,7 +88,7 @@ INLINE int evaluate_sysdiv(unsigned long freq)
        return i;
 }
 
-void clock_set_rate(void)
+void clock_init(void)
 {
        reg32_t rcc, rcc2;
        unsigned long clk;
@@ -113,7 +113,7 @@ void clock_set_rate(void)
        HWREG(SYSCTL_RCC) = rcc;
        HWREG(SYSCTL_RCC) = rcc2;
 
-       __delay(16);
+       lm3s_busyWait(16);
 
        /*
         * Step #2: select the crystal value (XTAL) and oscillator source
@@ -139,7 +139,7 @@ void clock_set_rate(void)
         HWREG(SYSCTL_RCC) = rcc;
        HWREG(SYSCTL_RCC) = rcc2;
 
-       __delay(16);
+       lm3s_busyWait(16);
 
        /*
         * Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and
@@ -171,5 +171,5 @@ void clock_set_rate(void)
 
        HWREG(SYSCTL_RCC) = rcc;
 
-       __delay(16);
+       lm3s_busyWait(16);
 }