LCD: generic OLED-RIT-128x96 (P14201) graphic display driver implementation.

[bertos.git] / bertos / cpu / cortex-m3 / drv / clock_lm3s.c

diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.c b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
index 8790b0e6ed69319fcdbf3f644a2417f0d199811a..1bc63f7ac24fdda41125a8f300c6db4f55d51d06 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
@@ -37,7 +37,7 @@
 
 #include <cfg/compiler.h>
 #include <cfg/debug.h>
-#include "io/lm3s.h"
+#include <io/lm3s.h>
 #include "clock_lm3s.h"
 
 /* The PLL VCO frequency is 400 MHz */
@@ -51,12 +51,15 @@
 /*
  * Very small delay: each loop takes 3 cycles.
  */
-INLINE void __delay(unsigned long iterations)
+void NAKED __delay(unsigned long iterations)
 {
+       register uint32_t __n asm("r0") = iterations;
+
        asm volatile (
-               "1:     subs    %0, #1\n\t"
-               "       bne 1b\n\t"
-               : "=r"(iterations) : : "memory", "cc");
+               "1: subs r0, #1\n\t"
+               "bne 1b\n\t"
+               "bx lr\n\t"
+               : : "r"(__n) : "memory", "cc");
 }
 
 unsigned long clock_get_rate(void)
@@ -110,6 +113,8 @@ void clock_set_rate(void)
        HWREG(SYSCTL_RCC) = rcc;
        HWREG(SYSCTL_RCC) = rcc2;
 
+       __delay(16);
+
        /*
         * Step #2: select the crystal value (XTAL) and oscillator source
         * (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL